IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
Symbol
tRISE/FALL
AllOutputs
Parameter
Condition(1)
Min.
0.2(2)
Max.
Unit
Rise/FallTime
Load = 50Ω to VCC/2, CL = 20pF
2
ns
(between0.8Vand2V)
OutputPulseWidth
Q, Q, Q/2 outputs(3) Q0-Q4, Q5, Q/2, @ 1.5V
(3)
tPULSEWIDTH
Load = 50Ω to VCC/2, CL = 20pF
0.5tCYCLE–0.8(5) 0.5tCYCLE+0.8(5)
0.5tCYCLE–1(5) 0.5tCYCLE+1(5)
ns
ns
ns
ps
ps
ps
ms
tPULSEWIDTH
2QOutput(3)
tPD
OutputPulseWidth
2Q @ 1.5V
SYNC input to FEEDBACK delay
Load = 50Ω to VCC/2, CL = 20pF
+0.1
—
+1.3
600
250
800
10
(3)
(5)
SYNC-FEEDBACK (measured at SYNC0 or 1 and FEEDBACK input pins) 0.1µF from LF to Analog GND
tSKEWr
(3,4)
OutputtoOutputSkewbetweenoutputs 2Q,Q0-Q4,
Q/2(risingedges only)
Load = 50Ω to VCC/2, CL = 20pF
(rising)
tSKEWf
OutputtoOutputSkew
—
(3,4)
(falling)
betweenoutputsQ0-Q4(fallingedgesonly)
OutputtoOutputSkew
tSKEWall(3,4)
—
2Q, Q/2, Q0-Q4 rising, Q5 falling
TimerequiredtoacquirePhase-Lockfromtime
SYNC input signal is received
OutputEnableTime
(6)
(2)
tLOCK
1
(2)
tPZH
tPZL
tPHZ
tPLZ
3
14
14
ns
ns
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
OutputDisableTime
(2)
3
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where C1 is loop filter
capacitor shown in Figure 2).
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration.
FREQ_SEL
Level
Feedback
Output
Q/2
Allowable SYNC Input
FrequencyRange(MHZ)
10to(2x_QfMAX Spec)/4
20 to (2x_Q fMAX Spec)/2
20 to (2x_Q fMAX Spec)/2
40 to (2x_Q fMAX Spec)
5 to (2x_Q fMAX Spec)/8
10 to (2x_QfMAX Spec)/4
10 to (2x_QfMAX Spec)/4
20 to (2x_Q fMAX Spec)/2
Corresponding 2Q Output
FrequencyRange
Phase Relationship of the Q Outputs
to Rising SYNC Edge
HIGH
HIGH
HIGH
HIGH
LOW
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
20 to (2QfMAX Spec)/2
20 to (2QfMAX Spec)/2
20 to (2QfMAX Spec)/2
20 to (2QfMAX Spec)/2
0°
0°
Any Q (Q0-Q4)
Q5
180°
0°
2X_Q
Q/2
0°
LOW
Any Q (Q0-Q4)
Q5
0°
LOW
180°
0°
LOW
2X_Q
5