IDT74FCT388915T
3.3VLOWSKEWPLL-BASEDCMOSCLOCKDRIVER(3-STATE)
COMMERCIALTEMPERATURERANGE
ThefrequencyrelationshipshownhereisapplicabletoallQoutputs(Q0,Q1,
Q2, Q3 and Q4).
50 MHz signal
25 MHz feedback signal
HIGH
1:2 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always runat2Xthe Q/2frequency, andthe 2Qoutputwillrunat4Xthe Q/2
Q4
2Q
OE/RST
Q5
12.5 MHz
signal
Q/2
Q3
FEEDBACK
LOW
REF_SEL
SYNC(0)
VCC(AN)
LF
25 MHz
input
25 MHz
"Q"
Clock
frequency.
FCT388915T
50 MHz signal
Outputs
12.5 MHz feedback signal
Q2
GND(AN)
HIGH
FQ_SEL
HIGH
Q0
Q1
PLL_EN
HIGH
2Q
Q/2
Q5
OE/RST
Q4
FEEDBACK
REF_SEL
LOW
12.5 MHz
input
25 MHz
"Q"
Clock
Outputs
Q3
Q2
SYNC(0)
VCC(AN)
LF
AllowableInputFrequencyRange:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
FCT388915T
Figure 3b. Wiring Diagram and Frequency Relationships With
Q4 Output Feedback
GND(AN)
FQ_SEL
PLL_EN
HIGH
Q0
Q1
2:1 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
HIGH
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequencywillequaltheSYNCfrequency. TheQ/2 output willalwaysrunat
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
AllowableInputFrequencyRange:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
50 MHz feedback signal
HIGH
Figure 3a. Wiring Diagram and Frequency Relationships With Q/
2 Output Feedback
OE/RST
Q4
2Q
Q5
12.5 MHz
input
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
Q/2
LOW
50 MHz
input
25 MHz
Q3
"Q"
Clock
1:1 INPUT TO "Q" OUTPUT
FREQUENCYRELATIONSHIP
FCT388915T
Outputs
Q2
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency(andtherestofthe"Q"outputs)willequaltheSYNCfrequency. The
Q/2 output willalways runat1/2theQfrequency,andthe2Qoutputwillrun
at2Xthe Qfrequency.
GND(AN)
FQ_SEL
Q0
Q1
PLL_EN
HIGH
HIGH
AllowableInputFrequencyRange:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With
2Q Output Feedback
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