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74FCT2373CTSOCTG4 PDF预览

74FCT2373CTSOCTG4

更新时间: 2024-02-04 06:33:29
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 847K
描述
Octal D-Type Transparent Latches with 3-State Outputs and Series Damping Resistors 20-SOIC -40 to 85

74FCT2373CTSOCTG4 技术参数

是否无铅:含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOIC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.36Is Samacsys:N
系列:FCTJESD-30 代码:R-PDSO-G20
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:4.7 ns传播延迟(tpd):5.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

74FCT2373CTSOCTG4 数据手册

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CY74FCT2373T  
8-BIT LATCH  
WITH 3-STATE OUTPUTS  
SCCS039B – SEPTEMBER 1994 – REVISED OCTOBER 2001  
Q OR SO PACKAGE  
(TOP VIEW)  
Function and Pinout Compatible With the  
Fastest Bipolar Logic  
25-Output Series Resistors Reduce  
Transmission-Line Reflection Noise  
OE  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
O
O
0
7
Reduced V  
Equivalent FCT Functions  
(Typically = 3.3 V) Version of  
D
0
D
D
OH  
7
6
D
1
O
1
O
O
D
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
6
5
O
2
D
2
5
4
D
D
3
I
Supports Partial-Power-Down Mode  
off  
O
3
GND  
O
Operation  
4
LE  
Matched Rise and Fall Times  
3-State Outputs  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Fully Compatible With TTL Input and  
Output Logic Levels  
12-mA Output Sink Current  
15-mA Output Source Current  
description  
The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is  
ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-termination  
resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the  
CY74FCT373T to reduce noise in an existing design.  
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the  
required setup times are latched when LE transitions from high to low. Data appears on the bus when the  
output-enable (OE) input is low. When OE is high, the bus output is in the high-impedance state. In this mode,  
data can be entered into the latches.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
SPEED  
(ns)  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QSOP – Q  
SOIC – SO  
Tape and reel  
Tube  
4.7  
4.7  
4.7  
5.2  
8
CY74FCT2373CTQCT  
CY74FCT2373CTSOC  
CY74FCT2373CTSOCT  
CY74FCT2373ATQCT  
CY74FCT2373TQCT  
FCT2373C  
FCT2373C  
–40°C to 85°C  
Tape and reel  
Tape and reel  
Tape and reel  
QSOP – Q  
QSOP – Q  
FCT2373A  
FCT2373  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74FCT2373CTSOCTG4 替代型号

型号 品牌 替代类型 描述 数据表
CY74FCT2373CTSOC TI

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