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74F539PC PDF预览

74F539PC

更新时间: 2024-09-29 22:49:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 55K
描述
Dual 1-of-4 Decoder with 3-STATE Outputs

74F539PC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, PLASTIC, MS-001, DIP-20
针数:20Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.69Is Samacsys:N
系列:F/FASTJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.075 mm
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.024 A
功能数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:CONFIGURABLE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):60 mA
Prop。Delay @ Nom-Sup:19.5 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

74F539PC 数据手册

 浏览型号74F539PC的Datasheet PDF文件第2页浏览型号74F539PC的Datasheet PDF文件第3页浏览型号74F539PC的Datasheet PDF文件第4页浏览型号74F539PC的Datasheet PDF文件第5页浏览型号74F539PC的Datasheet PDF文件第6页 
April 1988  
Revised August 1999  
74F539  
Dual 1-of-4 Decoder with 3-STATE Outputs  
General Description  
The 74F539 contains two independent decoders. Each  
accepts two Address (A0, A1) input signals and decodes  
them to select one of four mutually exclusive outputs. A  
polarity control input (P) determines whether the outputs  
are active HIGH (P = L) or active LOW (P = H). An active  
LOW input Enable (E) is available for data demultiplexing;  
data is routed to the selected output in non-inverted form in  
the active LOW mode or in inverted form in the active HIGH  
mode. A HIGH signal on the active LOW Output Enable  
(OE) input forces the 3-STATE outputs to the high imped-  
ance state.  
Ordering Code:  
Order Number Package Number  
Package Description  
74F539SC  
74F539PC  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS009552  
www.fairchildsemi.com  

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