5秒后页面跳转
74F192PC PDF预览

74F192PC

更新时间: 2024-02-01 23:17:40
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路光电二极管输出元件时钟
页数 文件大小 规格书
10页 195K
描述
Up/Down Decade Counter with Separate Up/Down Clocks

74F192PC 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82其他特性:TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
计数方向:BIDIRECTIONAL系列:F/FAST
JESD-30 代码:R-PDSO-G16长度:10.3 mm
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
传播延迟(tpd):13.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.5 mm
最小 fmax:125 MHzBase Number Matches:1

74F192PC 数据手册

 浏览型号74F192PC的Datasheet PDF文件第1页浏览型号74F192PC的Datasheet PDF文件第3页浏览型号74F192PC的Datasheet PDF文件第4页浏览型号74F192PC的Datasheet PDF文件第5页浏览型号74F192PC的Datasheet PDF文件第6页浏览型号74F192PC的Datasheet PDF文件第7页 
Unit Loading/Fan Out  
54F/74F  
Pin Names  
Description  
U.L.  
Input I /I  
IH IL  
HIGH/LOW Output I /I  
OH OL  
b
1.0/3.0 20 mA/ 1.8 mA  
CP  
CP  
Count Up Clock Input (Active Rising Edge)  
Count Down Clock Input (Active Rising Edge)  
Asynchronous Master Reset Input (Active HIGH)  
Asynchronous Parallel Load Input (Active LOW)  
Parallel Data Inputs  
U
D
b
1.0/3.0 20 mA/ 1.8 mA  
b
1.0/1.0 20 mA/ 0.6 mA  
MR  
PL  
b
1.0/1.0 20 mA/ 0.6 mA  
b
1.0/1.0 20 mA/ 0.6 mA  
P P  
0
3
b
b
b
Q Q  
0
Flip-Flop Outputs  
50/33.3  
1 mA/20 mA  
1 mA/20 mA  
1 mA/20 mA  
3
TC  
TC  
Terminal Count Down (Borrow) Output (Active LOW) 50/33.3  
Terminal Count Up (Carry) Output (Active LOW) 50/33.3  
D
U
Functional Description  
The ’F192 is an asynchronously presettable decade coun-  
ter. It contains four edge-triggered flip-flops, with internal  
gating and steering logic to provide master reset, individual  
preset, count up and count down operations.  
load operation, the next LOW-to-HIGH transition of that  
clock will be interpreted as a legitimate signal and will be  
counted.  
Function Table  
A LOW-to-HIGH transition on the CP input to each flip-flop  
causes the output to change state. Synchronous switching,  
as opposed to ripple counting, is achieved by driving the  
steering gates of all stages from a common Count Up line  
and a common Count Down line, thereby causing all state  
changes to be initiated simultaneously. A LOW-to-HIGH  
transition on the Count Up input will advance the count by  
one; a similar transition on the Count Down input will de-  
crease the count by one. While counting with one clock in-  
put, the other should be held HIGH, as indicated in the  
Function Table. Otherwise, the circuit will either count by  
twos or not at all, depending on the state of the first flip-flop,  
which cannot toggle as long as either clock input is LOW.  
MR  
PL  
CP  
CP  
Mode  
U
D
H
L
L
L
L
X
L
X
X
H
X
X
H
H
Reset (Asyn.)  
Preset (Asyn.)  
No Change  
Count Up  
H
H
H
L
H
L
Count Down  
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
e
L
LOW-to-HIGH Clock Transition  
State Diagram  
The Terminal Count Up (TC ) and Terminal Count Down  
U
(TC ) outputs are normally HIGH. When the circuit has  
D
reached the maximum count state 9, the next HIGH-to-LOW  
transition of the Count Up Clock will cause TC to go LOW.  
U
TC will stay LOW until CP goes HIGH again, thus effec-  
U
U
tively repeating the Count Up Clock, but delayed by two  
gate delays. Similarly, the TC output will go LOW when the  
D
circuit is in the zero state and the Count Down Clock goes  
LOW. Since the TC outputs repeat the clock waveforms,  
they can be used as the clock input signals to the next  
higher order circuit in a multistage counter.  
e
TC  
Q
Q
Q
Q
CP  
#
#
#
#
U
0
3
U
e
TC  
D
Q
Q
3
CP  
D
#
#
0
1
2
The ’F192 has an asynchronous parallel load capability per-  
mitting the counter to be preset. When the Parallel Load  
(PL) and the Master Reset (MR) inputs are LOW, informa-  
tion present on the Parallel Data input (P P ) is loaded  
3
0
into the counter and appears on the outputs regardless of  
the conditions of the clock inputs. A HIGH signal on the  
Master Reset input will disable the preset gates, override  
both clock inputs, and latch each Q output in the LOW state.  
If one of the clock inputs is LOW during and after a reset or  
TL/F/9496–4  
2

与74F192PC相关器件

型号 品牌 描述 获取价格 数据表
74F192PCQM FAIRCHILD Decade Counter, Synchronous, Bidirectional, TTL, PDIP16,

获取价格

74F192PCQR FAIRCHILD 暂无描述

获取价格

74F192QC FAIRCHILD 暂无描述

获取价格

74F192QCQR FAIRCHILD Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional,

获取价格

74F192SC NSC Up/Down Decade Counter with Separate Up/Down Clocks

获取价格

74F192SCQR FAIRCHILD Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional,

获取价格