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74F164A PDF预览

74F164A

更新时间: 2024-01-28 09:59:21
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
6页 62K
描述
Serial-In, Parallel-Out Shift Register

74F164A 技术参数

生命周期:Obsolete零件包装代码:QFN
包装说明:QCCJ,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61Is Samacsys:N
计数方向:RIGHT系列:F/FAST
JESD-30 代码:S-PQCC-J20长度:8.9662 mm
逻辑集成电路类型:SERIAL IN PARALLEL OUT位数:8
功能数量:1端子数量:20
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:POSITIVE EDGE
宽度:8.9662 mm最小 fmax:90 MHz
Base Number Matches:1

74F164A 数据手册

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Unit Loading/Fan Out  
Input IIH/IIL  
U.L.  
Pin Names  
Description  
Output IOH/IOL  
HIGH/LOW  
1.0/1.0  
A, B  
CP  
Data Inputs  
20 µA/0.6 mA  
20 µA/0.6 mA  
20 µA/0.6 mA  
1 mA/20 mA  
Clock Pulse Input (Active Rising Edge)  
Master Reset Input (Active LOW)  
Outputs  
1.0/1.0  
1.0/1.0  
MR  
Q0–Q7  
50/33.3  
Functional Description  
Mode Select Table  
The 74F164A is an edge-triggered 8-bit shift register with  
serial data entry and an output from each of the eight  
stages. Data is entered serially through one of two inputs  
(A or B); either of these inputs can be used as an active  
HIGH Enable for data entry through the other input. An  
unused input must be tied HIGH.  
Operating  
Inputs  
Outputs  
Q0  
Q1–Q7  
Mode  
MR  
L
A
X
l
B
X
l
Reset (Clear)  
L
L
L
L
H
L-L  
H
q0–q6  
q0–q6  
q0–q6  
q0–q6  
Each LOW-to-HIGH transition on the Clock (CP) input  
shifts data one place to the right and enters into Q0 the log-  
Shift  
H
l
h
l
H
h
h
ical AND of the two data inputs (A • B) that existed before  
the rising clock edge. A LOW level on the Master Reset  
(MR) input overrides all other inputs and clears the register  
asynchronously, forcing all Q outputs LOW.  
H
h
H(h) = HIGH Voltage Levels  
L(l) = LOW Voltage Levels  
X = Immaterial  
q
= Lower case letters indicate the state of the referenced input or output  
n
one setup time prior to the LOW-to-HIGH clock transition.  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2

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