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74F160AVC

更新时间： 2024-01-16 09:14:50
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
7页 75K
描述
Decade Counter, F/FAST Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, TTL, PDSO16, 0.300 INCH, SOIC-16

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74F160AVC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：compliant风险等级：5.92
计数方向：UPJESD-30 代码：R-PDIP-T16
JESD-609代码：e0负载/预设输入：YES
逻辑集成电路类型：DECADE COUNTER工作模式：SYNCHRONOUS
功能数量：1端子数量：16
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
子类别：Counters标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

74F160AVC 数据手册

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Functional Description  
The 74F160A and 74F162A count modulo-10 in the BCD  
(8421) sequence. From state 9 (HLLH) they increment to  
state 0 (LLLL). The clock inputs of all flip-flops are driven in  
parallel through a clock buffer. Thus all changes of the Q  
outputs (except due to Master Reset of the (F160A) occur  
as a result of, and synchronous with, the LOW-to-HIGH  
transition of the CP input signal. The circuits have four fun-  
damental modes of operation, in order of precedence:  
asynchronous reset (F160A), synchronous reset (F162A),  
parallel load, count-up and hold. Five control inputs—Mas-  
ter Reset (MR, F160A), Synchronous Reset (SR, F162A),  
Parallel Enable (PE), Count Enable Parallel (CEP) and  
Count Enable Trickle (CET)—determine the mode of oper-  
ation, as shown in the Mode Select Table. A LOW signal on  
MR overrides all other inputs and asynchronously forces all  
outputs LOW. A LOW signal on SR overrides counting and  
parallel loading and allows all outputs to go LOW on the  
next rising edge of CP. A LOW signal on PE overrides  
counting and allows information on the Parallel Data (Pn)  
The F160A and F162A use D-type edge-triggered flip-flops  
and changing the SR, PE, CEP and CET inputs when the  
CP is in either state does not cause errors, provided that  
the recommended setup and hold times, with respect to the  
rising edge of CP, are observed.  
The Terminal Count (TC) output is HIGH when CET is  
HIGH and counter is in state 9. To implement synchronous  
multistage counters, the TC outputs can be used with the  
CEP and CET inputs in two different ways. Please refer to  
the F568 data sheet. The TC output is subject to decoding  
spikes due to internal race conditions and is therefore not  
recommended for use as a clock or asynchronous reset for  
flip-flops, counters or registers. In the F160A and F162A  
decade counters, the TC output is fully decoded and can  
only be HIGH in state 9. If a decade counter is preset to an  
illegal state, or assumes an illegal state when power is  
applied, it will return to the normal sequence within two  
counts, as shown in the State Diagram.  
Logic Equations:  
inputs to be loaded into the flip-flops on the next rising  
edge of CP. With PE and MR (F160A) or SR (F162A)  
HIGH, CEP and CET permit counting when both are HIGH.  
Conversely, a LOW signal on either CEP or CET inhibits  
counting.  
Count Enable = CEP × CET × PE  
TC = Q0 × Q 1× Q 2 × Q3 × CET  
Mode Select Table  
State Diagram  
Action on the Rising  
*SR PE CET CEP  
Clock Edge (  
Reset (Clear)  
)
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
Load (Pn → Qn)  
Count (Increment)  
No Change (Hold)  
No Change (Hold)  
H
H
H
X
*For 74’F162A only  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
3
www.fairchildsemi.com  
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