5秒后页面跳转
74AUP1G97GN PDF预览

74AUP1G97GN

更新时间: 2024-02-05 16:43:29
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
20页 295K
描述
Low-power configurable multiple function gateProduction

74AUP1G97GN 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:XSON-6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
系列:AUP/ULP/VJESD-30 代码:R-PDSO-N6
JESD-609代码:e3长度:1 mm
逻辑集成电路类型:LOGIC CIRCUIT湿度敏感等级:1
功能数量:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:0.35 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.1 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.3 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:0.9 mmBase Number Matches:1

74AUP1G97GN 数据手册

 浏览型号74AUP1G97GN的Datasheet PDF文件第2页浏览型号74AUP1G97GN的Datasheet PDF文件第3页浏览型号74AUP1G97GN的Datasheet PDF文件第4页浏览型号74AUP1G97GN的Datasheet PDF文件第5页浏览型号74AUP1G97GN的Datasheet PDF文件第6页浏览型号74AUP1G97GN的Datasheet PDF文件第7页 
74AUP1G97  
Low-power configurable multiple function gate  
Rev. 13 — 9 May 2023  
Product data sheet  
1. General description  
The 74AUP1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device  
can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter  
and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device  
ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to  
3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
CMOS low power dissipation  
High noise immunity  
ESD protection:  
HBM JESD22-A114F exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
Low static power consumption; ICC = 0.9 μA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Overvoltage tolerant inputs to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

与74AUP1G97GN相关器件

型号 品牌 描述 获取价格 数据表
74AUP1G97GN,132 NXP 74AUP1G97 - Low-power configurable multiple function gate SON 6-Pin

获取价格

74AUP1G97GS NXP Low-power configurable multiple function gate

获取价格

74AUP1G97GS NEXPERIA Low-power configurable multiple function gateProduction

获取价格

74AUP1G97GW NXP Low-power configurable multiple function gate

获取价格

74AUP1G97GW NEXPERIA Low-power configurable multiple function gateProduction

获取价格

74AUP1G97GX NEXPERIA Low-power configurable multiple function gateProduction

获取价格