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74AUP1G95L6X PDF预览

74AUP1G95L6X

更新时间: 2022-05-17 14:18:14
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD
页数 文件大小 规格书
10页 577K
描述
TinyLogic® Low Power Universal Configurable Two-Input Logic Gate (Open Drain Output)

74AUP1G95L6X 数据手册

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Logic Configurations  
Figure 2 through Figure 8 show the logical functions that  
can be implemented using the 74AUP1G95. The  
diagrams show the DeMorgan’s equivalent logic duals  
implementation is next to the board-level physical  
implementation of how the pins should be connected.  
for  
a
given two-input function. The logical  
VCC  
VCC  
C
B
A
1
2
3
6
5
4
C
Y
B
A
Y
1
2
3
6
5
4
C
Y
C
A
Y
A
GND  
Notes:  
GND  
2. When C is L, Y=B.  
3. When C is H, Y=A.  
Figure 2.  
2-to-1 MUX  
Figure 3.  
2-Input AND Gate  
VCC  
VCC  
C
B
Y
Y
C
A
Y
Y
1
2
3
6
5
4
C
Y
B
1
2
3
6
C
Y
C
B
5
4
C
A
A
GND  
GND  
Figure 4.  
2-Input OR Gate with One Inverted  
Input  
Figure 5.  
2-Input AND Gate with One Inverted  
Input  
2-Input NAND Gate with One Inverted Input  
2-Input NOR Gate with One Inverted Input  
VCC  
VCC  
1
2
3
6
5
4
C
Y
C
B
1
2
3
6
5
4
C
Y
B
C
Y
Y
GND  
GND  
Figure 6.  
2-Input OR Gate  
Figure 7.  
Inverter  
VCC  
B
1
6
5
4
B
Y
2
3
Y
GND  
Figure 8.  
Buffer  
© 2008 Fairchild Semiconductor Corporation  
74AUP1G95 • Rev. 1.0.1  
www.fairchildsemi.com  
3

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