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74ALS174 PDF预览

74ALS174

更新时间: 2024-01-20 01:38:55
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
8页 101K
描述
Hex D flip-flop

74ALS174 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.41Is Samacsys:N
系列:ALSJESD-30 代码:R-PDIP-T16
长度:19.025 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP位数:6
功能数量:1端子数量:16
最高工作温度:70 °C最低工作温度:
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):14 mA
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:4.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:60 MHzBase Number Matches:1

74ALS174 数据手册

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Philips Semiconductors  
Product specification  
Hex D flip-flop  
74ALS174  
FEATURES  
PIN CONFIGURATION  
Four edge-triggered D flip-flops  
MR  
Q0  
D0  
D1  
Q1  
1
2
3
4
5
16  
V
Buffered common clock  
CC  
15 Q5  
14 D5  
13 D4  
12 Q4  
11 D3  
10 Q3  
Buffered asynchronous master reset  
DESCRIPTION  
The 74ALS174 has six edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered clock (CP)  
and master reset (MR) inputs load and reset (clear) all flip-flops  
simultaneously.  
D2  
Q2  
6
7
8
GND  
9
CP  
The register is fully edge-triggered. The state of each D input, one  
setup time before the Low-to-High clock transition is transferred to  
the corresponding flip-flop’s Q output.  
SF00188  
All Q outputs will be forced Low independent of clock or data inputs  
by a Low voltage level on the MR input. The device is useful for  
applications where true outputs only are required, and the clock and  
master reset are common to all storage elements.  
ORDERING INFORMATION  
ORDER CODE  
DRAWING  
NUMBER  
DESCRIPTION  
COMMERCIAL RANGE  
V
amb  
= 5V ±10%,  
= 0°C to +70°C  
CC  
TYPICAL  
TYPICAL  
T
SUPPLY CURRENT  
(TOTAL)  
TYPE  
f
MAX  
16-pin plastic DIP  
16-pin plastic SO  
74ALS174N  
74ALS174D  
SOT38-4  
74ALS174  
70MHz  
7mA  
SOT109-1  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
74ALS (U.L.)  
LOAD VALUE  
PINS  
DESCRIPTION  
HIGH/LOW  
1.0/1.0  
1.0/1.0  
1.0/1.0  
20/80  
HIGH/LOW  
20µA/0.1mA  
20µA/0.1mA  
20µA/0.1mA  
0.4mA/8mA  
D0 – D3  
CP  
Data inputs  
Clock Pulse input (active rising edge)  
Master Reset input (active-Low)  
Data outputs  
MR  
Q0 – Q5  
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.  
LOGIC SYMBOL  
IEC/IEEE SYMBOL  
3
4
6
11  
13  
14  
9
1
C1  
R
D0 D1 D2 D3  
D4 D5  
3
2
5
1D  
9
1
CP  
MR  
4
6
7
Q0 Q1 Q2  
Q3  
Q4 Q5  
11  
13  
14  
10  
12  
15  
2
5
7
10 12  
15  
V
= Pin 16  
CC  
GND = Pin 8  
SF00190  
SF00189  
2
1991 Feb 08  
853–1023 01670  

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