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74ALS191

更新时间： 2024-02-12 04:48:25
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
8页 135K
描述
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

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74ALS191 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
风险等级：5.9计数方向：BIDIRECTIONAL
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
负载/预设输入：YES逻辑集成电路类型：BINARY COUNTER
最大频率@ Nom-Sup：30000000 Hz最大I（ol）：0.008 A
工作模式：SYNCHRONOUS功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V最大电源电流（ICC）：22 mA
认证状态：Not Qualified子类别：Counters
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

74ALS191 数据手册

 浏览型号74ALS191的Datasheet PDF文件第2页浏览型号74ALS191的Datasheet PDF文件第3页浏览型号74ALS191的Datasheet PDF文件第4页浏览型号74ALS191的Datasheet PDF文件第5页浏览型号74ALS191的Datasheet PDF文件第6页浏览型号74ALS191的Datasheet PDF文件第7页 
SN54ALS191A, SN74ALS191A  
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS  
SDAS210C – DECEMBER 1982 – REVISED JULY 1996  
SN54ALS191A . . . J PACKAGE  
SN74ALS191A . . . D OR N PACKAGE  
Single Down/Up Count-Control Line  
Look-Ahead Circuitry Enhances Speed of  
Cascaded Counters  
(TOP VIEW)  
Fully Synchronous in Count Modes  
B
V
A
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Q
Q
Asynchronously Presettable With Load  
Control  
B
A
CLK  
RCO  
MAX/MIN  
LOAD  
C
CTEN  
D/U  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
Q
C
Q
D
GND  
D
description  
SN54ALS191A . . . FK PACKAGE  
(TOP VIEW)  
The ’ALS191A are synchronous 4-bit reversible  
up/down binary counters. Synchronous counting  
operation is provided by having all flip-flops  
clocked simultaneously so that the outputs  
change coincidentally with each other when  
instructed by the steering logic. This mode of  
operation eliminates the output counting spikes  
3
2
1
20 19  
18  
CLK  
Q
4
5
6
7
8
A
RCO  
CTEN  
NC  
17  
16  
15  
14  
NC  
normally  
associated  
with  
asynchronous  
MAX/MIN  
LOAD  
D/U  
(ripple-clock) counters.  
Q
C
The outputs of the four flip-flops are triggered on  
a low-to-high-level transition of the clock (CLK)  
input if the count enable (CTEN) input is low. A  
high at CTEN inhibits counting. The direction of  
the count is determined by the level of the  
down/up (D/U) input. When D/Uislow, thecounter  
counts up, and when D/U is high, the counter  
counts down.  
9 10 11 12 13  
NC – No internal connection  
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter is dictated solely by the conditions meeting the stable setup and hold times.  
These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD  
input and entering the desired data at the data inputs. The output changes to agree with the data inputs  
independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers  
by simply modifying the count length with the preset inputs.  
CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on  
(current required by) clock drivers, for long parallel words.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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