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74ACT244TTR PDF预览

74ACT244TTR

更新时间: 2024-01-26 03:42:02
品牌 Logo 应用领域
其他 - ETC 驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 71K
描述
Dual 4-Bit Non-Inverting Buffer/Driver

74ACT244TTR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.05
控制类型:ENABLE LOW系列:ACT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74ACT244TTR 数据手册

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74ACT244  
OCTAL BUS BUFFER  
WITH 3 STATE OUTPUTS (NON INVERTED)  
HIGH SPEED: t = 4.6 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS  
= 2V (MIN.), V = 0.8V (MAX.)  
50TRANSMISSION LINE DRIVING  
V
IH  
IL  
DIP  
SOP  
TSSOP  
T & R  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
DIP  
SOP  
74ACT244B  
74ACT244M  
V
CC  
74ACT244MTR  
74ACT244TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 244  
IMPROVED LATCH-UP IMMUNITY  
TSSOP  
memory address drivers, etc.  
DESCRIPTION  
The device is designed to interface directly High  
Speed CMOS systems with TTL, NMOS and  
CMOS output voltage levels.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74ACT244 is an advanced high-speed CMOS  
OCTAL BUS BUFFER (3-STATE) fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS tecnology.  
The G input controls four BUS BUFFERs.  
This device is designed to be used with 3 state  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2001  
1/9  

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