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74AC191SCX

更新时间： 2024-01-20 02:08:51

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器触发器逻辑集成电路光电二极管输出元件
页数	文件大小	规格书
10页	117K
描述
Asynchronous Up/Down Counter

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技术参数
数据手册

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74AC191SCX 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	5.30 MM, EIAJ TYPE2, SOP-16
针数：	16	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.66
其他特性：	TCO OUTPUT	计数方向：	BIDIRECTIONAL
系列：	AC	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	10.2 mm
负载电容（CL）：	50 pF	负载/预设输入：	YES
逻辑集成电路类型：	BINARY COUNTER	最大频率@ Nom-Sup：	65000000 Hz
最大I（ol）：	0.012 A	工作模式：	SYNCHRONOUS
湿度敏感等级：	1	位数：	4
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.3	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	包装方法：	TAPE AND REEL
峰值回流温度（摄氏度）：	260	电源：	3.3/5 V
传播延迟（tpd）：	16 ns	认证状态：	Not Qualified
座面最大高度：	2.1 mm	子类别：	Counters
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	2 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	触发器类型：	POSITIVE EDGE
宽度：	5.3 mm	最小 fmax：	133 MHz
Base Number Matches：	1

74AC191SCX 数据手册

RC Truth Table

Inputs

Outputs

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition

= Clock Pulse

(Note 1)

Note 1: TC is generated internally

Functional Description

The AC191 is a synchronous up/down counter. The AC191

is organized as a 4-bit binary counter. It contains four edge-

triggered flip-flops with internal gating and steering logic to

provide individual preset, count-up and count-down opera-

tions.

ripple through to the last stage before the clock goes HIGH.

There is no such restriction on the HIGH state duration of

the clock, since the RC output of any device goes HIGH

shortly after its CP input goes HIGH.

The configuration shown in Figure 3 avoids ripple delays

and their associated restrictions. The CE input for a given

stage is formed by combining the TC signals from all the

preceding stages. Note that in order to inhibit counting an

enable signal must be included in each carry gate. The

simple inhibit scheme of Figure 1 and Figure 2 doesn't

apply, because the TC output of a given stage is not

affected by its own CE.

Each circuit has an asynchronous parallel load capability

permitting the counter to be preset to any desired number.

When the Parallel Load (PL) input is LOW, information

present on the Parallel Load inputs (P₀–P₃) is loaded into

the counter and appears on the Q outputs. This operation

overrides the counting functions, as indicated in the Mode

Select Table.

A HIGH signal on the CE input inhibits counting. When CE

is LOW, internal state changes are initiated synchronously

by the LOW-to-HIGH transition of the clock input. The

direction of counting is determined by the U/D input signal,

as indicated in the Mode Select Table. CE and U/D can be

changed with the clock in either state, provided only that

the recommended setup and hold times are observed.

Mode Select Table

Inputs

U/D

Mode

Count Up

Two types of outputs are provided as overflow/underflow

indicators. The terminal count (TC) output is normally

LOW. It goes HIGH when the circuits reach zero in the

count down mode or 15 in the count up mode. The TC out-

put will then remain HIGH until a state change occurs,

whether by counting or presetting or until U/D is changed.

The TC output should not be used as a clock signal

because it is subject to decoding spikes.

Count Down

Preset (Asyn.)

No Change (Hold)

State Diagram

The TC signal is also used internally to enable the Ripple

Clock (RC) output. The RC output is normally HIGH. When

CE is LOW and TC is HIGH, RC output will go LOW when

the clock next goes LOW and will stay LOW until the clock

goes HIGH again. This feature simplifies the design of mul-

tistage counters, as indicated in Figure 1 and Figure 2. In

Figure 1, each RC output is used as the clock input for the

next higher stage. This configuration is particularly advan-

tageous when the clock source has a limited drive capabil-

ity, since it drives only the first stage. To prevent counting in

all stages it is only necessary to inhibit the first stage, since

a HIGH signal on CE inhibits the RC output pulse, as indi-

cated in the RC Truth Table. A disadvantage of this config-

uration, in some applications, is the timing skew between

state changes in the first and last stages. This represents

the cumulative delay of the clock as it ripples through the

preceding stages.

A method of causing state changes to occur simulta-

neously in all stages is shown in Figure 2. All clock inputs

are driven in parallel and the RC outputs propagate the

carry/borrow signals in ripple fashion. In this configuration

the LOW state duration of the clock must be long enough to

allow the negative-going edge of the carry/borrow signal to

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与74AC191SCX相关器件

型号	品牌	描述	获取价格	数据表
74AC191SCX_NL	FAIRCHILD	Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMO	获取价格
74AC191SCXR	FAIRCHILD	Binary Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMO	获取价格
74AC191SJ	FAIRCHILD	Up/Down Counter with Preset and Ripple Clock	获取价格
74AC191SJ	TI	AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16, 0.300 I	获取价格
74AC191SJX	FAIRCHILD	Asynchronous Up/Down Counter	获取价格
74AC192DCQR	FAIRCHILD	Decade Counter, AC Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMO	获取价格

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