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74LS10

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74LS10 技术参数

August 1986

Revised March 2000

DM74LS10

Triple 3-Input NAND Gate

General Description

This device contains three independent gates each of

which performs the logic NAND function.

Ordering Code:

Order Number Package Number

Package Description

DM74LS10M

DM74LS10N

M14A

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Y = ABC

Inputs

Output

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

DS006349

www.fairchildsemi.com

12 3 4

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型号	品牌	描述	获取价格	数据表
74LS107A	NXP	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14	获取价格
74LS107DC	FAIRCHILD	Jbar-Kbar Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDIP14,	获取价格
74LS107F	NXP	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14	获取价格
74LS107FCQM	FAIRCHILD	Jbar-Kbar Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDFP14,	获取价格
74LS107FCQR	FAIRCHILD	Jbar-Kbar Flip-Flop, 2-Func, Master-slave Triggered, TTL, CDFP14,	获取价格
74LS107PCQM	FAIRCHILD	Jbar-Kbar Flip-Flop, 2-Func, Master-slave Triggered, TTL, PDIP14,	获取价格