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73S8023C-IM/F PDF预览

73S8023C-IM/F

更新时间: 2024-02-11 05:29:35
品牌 Logo 应用领域
TERIDIAN 模拟IC信号电路
页数 文件大小 规格书
27页 383K
描述
Smart Card Interface

73S8023C-IM/F 技术参数

生命周期:Transferred包装说明:5 X 5 MM, LEAD FREE, QFN-32
Reach Compliance Code:unknown风险等级:5.59
Is Samacsys:N模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:S-XQCC-N32长度:5 mm
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态:Not Qualified座面最大高度:0.9 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:5 mm
Base Number Matches:1

73S8023C-IM/F 数据手册

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73S8023C Data Sheet  
DS_8023C_019  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Unit  
Reset and Clock for card interface, RST, CLK  
VOH  
VOL  
Output level, high  
Output level, low  
0.9 VCC  
0
VCC  
0.2  
0.1  
0.3  
30  
V
V
IOH = -200 µA  
IOL= 200 µA  
IOL = 0  
V
Output voltage when outside  
of a session  
VINACT  
IOL = 1 mA  
V
IRST_LIM Output current limit, RST  
ICLK_LIM Output current limit, CLK  
mA  
mA  
70  
CL = 35 pF for  
CLK, 10% to 90%  
8
ns  
ns  
tR, tF  
Output rise time, fall time  
CL = 200 pF for  
RST, 10% to 90%  
100  
CLKSEL = 1, Cap.  
load on CLK and  
RST is minimal,  
else rise, fall times  
are a factor  
Delay time STROBE to CLK,  
RSTIN to RST  
Td  
20  
55  
ns  
%
CL = 35 pF,  
48% < δIN < 52%  
Duty cycle for CLK  
45  
δ
12.5 Digital Signals  
Symbol  
Parameter  
Condition  
Min  
Typ  
Max  
Unit  
Digital I/O Except for OSC I/O  
VIL  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
Pull-up resistor, OFF  
-0.3  
1.8  
0.8  
VDD + 0.3  
0.45  
V
V
VIH  
VOL  
VOH  
ROUT  
IOL = 2 mA  
IOH = -1 mA  
V
VDD - 0.45  
V
20  
kΩ  
Time from CS going high to  
interface active  
tSL  
tDZ  
tIS  
tSI  
tID  
tDI  
50  
50  
50  
ns  
ns  
ns  
ns  
ns  
Time from CS going low to  
interface inactive, Hi-Z  
Set-up time, control signals  
to CS rising edge  
Hold time, control signals  
from CS rising edge  
50  
Set-up time, control signals  
to CS fall  
50  
-5  
Hold time, control signals  
from CS fall  
50  
5
ns  
|IIL1  
|
Input Leakage Current  
GND < VIN < VDD  
μA  
22  
Rev. 1.5  
 

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