Datasheet > 73S8014RT-ILR/F2

73S8014RT-ILR/F2

更新时间： 2024-02-04 14:56:41

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描述
Analog Circuit

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技术参数
数据手册

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73S8014RT-ILR/F2 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.64
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	峰值回流温度（摄氏度）：	NOT SPECIFIED
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

73S8014RT-ILR/F2 数据手册

73S8014R Data Sheet

DS_8014R_012

Table 1 provides the 73S8014R pin names, pin numbers, type, equivalent circuits and descriptions.

Table 1: 73S8014R 20-Pin SOP Pin Definitions

Number

Equivalent

Circuit

Pin Name

Type

Description

Card Interface

Card I/O: Data signal to/from card. Includes an 11k pull-up

resistor to V_CC.

I/O

Figure 14

RST

Figure 13 Card reset: provides reset (RST) signal to card.

Card clock: provides clock signal (CLK) to card. The rate of this

clock is determined by the external crystal frequency or frequency

of the external clock signal applied on XTALIN and CLKDIV

selections.

CLK

Figure 12

Card Presence switch: active high indicates card is present.

Figure 16

PRES

Includes a high-impedance pull-down current source.

Card power supply – logically controlled by sequencer, output of

Figure 11 LDO regulator. Requires an external filter capacitor to the card

GND.

VCC

GND

PSO

GND

–

Card ground.

Host Processor Interface

Command VCC (negative assertion): Logic low on this pin causes

CMDVCC

Figure 16 the LDO regulator to ramp the V_CCsupply to the card and initiates

a card activation sequence, if a card is present.

5 volt / 3 volt card selection: Logic one selects 5 volts for V_CCand

card interface, logic low selects 3 volt operation. When the part is

to be used with a single card voltage, this pin should be tied to

either GND or V_DD. However, it includes a high impedance pull-up

5V/#V

Figure 16

resistor to default this pin high (selection of 5V card) when not

connected. This pin shall not be changed when CMDVCC is low.

Sets the divide ratio from the XTAL oscillator (or external clock

input) to the card clock. These pins include a pull-up resistor for

CLKDIV1 and CLKLDIV2 to provide a default rate of divide by

two.

CLKDIV1

CLKDIV2

CLKDIV1

CLKDIV2

CLOCK RATE

XTALIN/8

XTALIN/4

XTALIN/2

XTALIN

Figure 16

Interrupt signal to the processor. Active Low - Multi-function

OFF

Figure 10 indicating fault conditions and card presence. Open drain output

configuration – It includes an internal 20kΩ pull-up to V_DD.

RSTIN

I/OUC

Figure 16 Reset Input: This signal is the reset command to the card.

System controller data I/O to/from the card. Includes an 11K

Figure 15

pull-up resistor to V_DD.

Rev. 1.0

1...3 4 567 8 9...29

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