73M2901CL
V.22bis Single Chip Modem
SPECIFYING A CRYSTAL
Crystals with low ESRs may oscillate at higher than
specified voltage levels.
The manufacturer of a crystal resonator verifies its
frequency of oscillation in a test set-up, but to
ensure that the same frequency is obtained in the
application, the circuit conditions must be the same.
The TDK 73M2901CL modem requires a parallel
mode (anti-resonant) crystal, the important
specifications of which are as follows:
RESET
A reset is accomplished by holding the RESET pin
high. To ensure a proper power-on reset, the reset
pin must be held high for a minimum of 3µs. At
power on, the voltage at VPD, VPA, and RESET
must come up at the same time for a proper reset.
The signals '&', &76 and '65 will be held inactive
for 25ms, acknowledging the reset operation, within
a 250ms time window after the reset-triggering
event. The 73M2901CL is ready for operation after
that 250ms window and/or after the signals '&',
&76 and '65 become active.
Mode:
Parallel (anti-resonant)
11.0592 MHz
Frequency:
Frequency tolerance:
±50 ppm at initial temperature.
Temperature drift:
An additional ±50 ppm over full range.
ASYNCHRONOUS AND SYNCHRONOUS SERIAL
DATA INTERFACE
Load capacitance:
18pF or 20pF
75Ω max.
ESR:
The serial data interface consists of the TXD and
RXD data paths (LSB shifted in and out first,
respectively); and the TXCLK and RXCLK serial
clock outputs associated with the data pins;
&76/576 flow control; '&', '65 and '75. In
synchronous mode, the data is passed at the bit rate
(tolerance is +1%, -2.5%).
Drive level:
Less than 1mW.
The peak voltage level of the oscillator should be
checked to assure it will not violate the maximum
voltage levels allowed on the oscillator pins.
A
resistor in series with the crystal can be used, if
necessary, to reduce the oscillator’s peak voltage
levels.
PIN DESCRIPTIONS
POWER PIN DESCRIPTION
PIN
NAME
32 pin
PLCC
32 pin
TQFP
44 pin LQFP
TYPE DESCRIPTION
VPA
VNA
VPD
VND
15
21
10
16
16
I
I
I
I
Positive analog voltage (Analog supply)
Negative analog voltage (Analog ground)
Positive digital voltage (Digital supply)
Negative digital voltage (Digital ground)
22
6, 25, 29 2, 20, 25
5, 22, 26 1, 17, 22
2, 12, 27, 33
11, 24, 44, 28
ANALOG INTERFACE PIN DESCRIPTION
PIN
NAME
32 pin
PLCC
32 pin
TQFP
44 pin LQFP
TYPE DESCRIPTION
RXA
20
16
17
15
11
12
21
17
18
I
Receive Analog input
TXAN
TXAP
O
O
Transmit Analog - output
Transmit Analog + output
Analog Band Gap voltage reference (0.1µF to
VNA). This pin must not be connected to external
circuitry other than the decoupling capacitor.
VBG
19
18
14
13
20
19
O
O
Analog reference voltage (0.1µF to VNA)
VREF
3