73M2901CL

更新时间： 2024-01-27 14:12:11

品牌	Logo	应用领域
东电化 - TDK		调制解调器
页数	文件大小	规格书
18页	283K
描述
V.22 BIS SINGLE CHIP MODEM

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技术参数
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73M2901CL 技术参数

生命周期：	Obsolete	包装说明：	LEAD FREE, PLASTIC, LCC-32
Reach Compliance Code：	unknown	风险等级：	5.56
数据速率：	2.4 Mbps	JESD-30 代码：	R-PQCC-J32
长度：	13.995 mm	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
座面最大高度：	3.56 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	MODEM
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.455 mm	Base Number Matches：	1

73M2901CL 数据手册

73M2901CL

V.22bis Single Chip Modem

SPECIFYING A CRYSTAL

Crystals with low ESRs may oscillate at higher than

specified voltage levels.

The manufacturer of a crystal resonator verifies its

frequency of oscillation in a test set-up, but to

ensure that the same frequency is obtained in the

application, the circuit conditions must be the same.

The TDK 73M2901CL modem requires a parallel

mode (anti-resonant) crystal, the important

specifications of which are as follows:

RESET

A reset is accomplished by holding the RESET pin

high. To ensure a proper power-on reset, the reset

pin must be held high for a minimum of 3µs. At

power on, the voltage at VPD, VPA, and RESET

must come up at the same time for a proper reset.

The signals '&', &76 and '65 will be held inactive

for 25ms, acknowledging the reset operation, within

a 250ms time window after the reset-triggering

event. The 73M2901CL is ready for operation after

that 250ms window and/or after the signals '&',

&76 and '65 become active.

Mode:

Parallel (anti-resonant)

11.0592 MHz

Frequency:

Frequency tolerance:

±50 ppm at initial temperature.

Temperature drift:

An additional ±50 ppm over full range.

ASYNCHRONOUS AND SYNCHRONOUS SERIAL

DATA INTERFACE

Load capacitance:

18pF or 20pF

75Ω max.

ESR:

The serial data interface consists of the TXD and

RXD data paths (LSB shifted in and out first,

respectively); and the TXCLK and RXCLK serial

clock outputs associated with the data pins;

&76/576 flow control; '&', '65 and '75. In

synchronous mode, the data is passed at the bit rate

(tolerance is +1%, -2.5%).

Drive level:

Less than 1mW.

The peak voltage level of the oscillator should be

checked to assure it will not violate the maximum

voltage levels allowed on the oscillator pins.

resistor in series with the crystal can be used, if

necessary, to reduce the oscillator’s peak voltage

levels.

PIN DESCRIPTIONS

POWER PIN DESCRIPTION

NAME

32 pin

PLCC

32 pin

TQFP

44 pin LQFP

TYPE DESCRIPTION

VPA

VNA

VPD

VND

Positive analog voltage (Analog supply)

Negative analog voltage (Analog ground)

Positive digital voltage (Digital supply)

Negative digital voltage (Digital ground)

6, 25, 29 2, 20, 25

5, 22, 26 1, 17, 22

2, 12, 27, 33

11, 24, 44, 28

ANALOG INTERFACE PIN DESCRIPTION

NAME

32 pin

PLCC

32 pin

TQFP

44 pin LQFP

TYPE DESCRIPTION

RXA

Receive Analog input

TXAN

TXAP

Transmit Analog - output

Transmit Analog + output

Analog Band Gap voltage reference (0.1µF to

VNA). This pin must not be connected to external

circuitry other than the decoupling capacitor.

VBG

Analog reference voltage (0.1µF to VNA)

VREF

1 234 5 6 7...18

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