IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
INDEX
INDEX
4
3
2
32 31 30
1
29 28 27 26 25
32 31 30
D1
29
28
27
26
25
24
23
22
21
RS
5
1
2
3
4
D
1
24
23
22
21
20
19
18
17
D
0
WEN1
WEN1
WCLK
WEN2/LD
6
D0
WCLK
PAF
PAE
7
PAF
WEN2/LD
8
PAE
GND
VCC
9
VCC
GND
REN1
RCLK
REN2
OE
5
Q8
Q8
10
11
12
13
REN1
Q7
6
7
8
Q7
RCLK
Q6
Q6
REN2
Q5
Q5
9
10 11 12 13 14 15 16
14 15 16 17 18 19 20
2655 drw 02
2655 drw02a
TQFP (PR32-1, order code: PF)
TOP VIEW
PLCC (J32-1, order code: J)
TOP VIEW
PINDESCRIPTIONS
Symbol
D0-D8
RS
Name
I/O
Description
DataInputs
I
I
Datainputsfora9-bitbus.
Reset
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK
WriteClock
I
I
DataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLKwhentheWriteEnable(s)areasserted.
WEN1
WriteEnable1
If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW,
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables, WEN1 mustbeLOWandWEN2mustbeHIGHtowritedataintotheFIFO. Datawillnotbewritteninto
the FIFO if the FF is LOW.
WEN2/
LD
WriteEnable2/
Load
I
The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH
atreset, this pin operates as a second write enable. If WEN2/LD isLOW at reset, thispin operatesasa control
toloadandreadtheprogrammableflagoffsets. IftheFIFOisconfiguredtohavetwowriteenables, WEN1 must
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is
LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the
programmableflagoffsets.
Q0-Q8
RCLK
REN1
DataOutputs
ReadClock
O
I
Dataoutputsfora9-bitbus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
Read Enable 1
I
REN2
OE
Read Enable 2
OutputEnable
EmptyFlag
I
When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
I
state.
EF
O
O
O
O
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the
FIFO is not empty. EF is synchronized to RCLK.
WhenPAE isLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault
offsetatresetisEmpty+7. PAE issynchronizedtoRCLK.
WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffset
at reset is Full-7. PAF is synchronized to WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
isnotfull. FF issynchronizedtoWCLK.
PAE
PAF
FF
Programmable
Almost-EmptyFlag
Programmable
Almost-FullFlag
Full Flag
VCC
Power
One +5 volt power supply pin.
One 0 volt ground pin.
GND
Ground
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