Datasheet > 72421L15J

72421L15J

更新时间： 2023-02-26 15:49:53

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	126K
描述
PLCC-32, Tube

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数据手册

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72421L15J 数据手册

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe

A read and write should not be performed simultaneously to the offset

WriteEnable2/Load(WEN2/LD)pinissetLOWandbothReadEnables(REN1, registers.

REN2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransitionofthe

Read Clock (RCLK).

IDT72421 - 64 x 9-BIT

IDT72201 - 256 x 9-BIT

6 5

Empty Offset (LSB) Reg.

Default Value 007H

6 5

Full Offset (LSB) Reg.

Default Value 007H

Full Offset (LSB) Reg.

Default Value 007H

IDT72211 - 512 x 9-BIT

IDT72221 - 1,024 x 9-BIT

Empty Offset (LSB) Reg.

Default Value 007H

Empty Offset (LSB)

Default Value 007H

(MSB)

Full Offset (LSB) Reg.

Default Value 007H

Full Offset (LSB)

Default Value 007H

(MSB)

IDT72231 - 2,048 x 9-BIT

IDT72241 - 4,096 x 9-BIT

IDT72251 8,192 x 9-BIT

Empty Offset (LSB) Reg.

Default Value 007H

Empty Offset (LSB)

Default Value 007H

(MSB)

000

0000

00000

Full Offset (LSB)

Full Offset (LSB) Reg.

Default Value 007H

(MSB)

000

0000

00000

2655 drw 05

Figure 3. Offset Register Location and Default Values

OCTOBER22,2008

1...3 4 567 8 9...14

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