128K x 36, 256K x 18
IDT71V35761S
IDT71V35781S
IDT71V35761SA
IDT71V35781SA
3.3VSynchronousSRAMs
3.3VI/O,PipelinedOutputs
BurstCounter,SingleCycleDeselect
Features
Description
◆
128K x 36, 256K x 18 memory configurations
The IDT71V35761/781 are high-speed SRAMs organized as
128Kx36/256Kx18.TheIDT71V35761/781SRAMscontainwrite,data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof
thewritecycle.
◆
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
CommercialandIndustrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
LBO input selects interleaved or linear burst mode
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheIDT71V35761/81canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
◆
◆
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
◆
◆
◆
◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1 orderofthesethreeaddressesaredefinedbytheinternalburstcounter
compliant)
andthe LBO inputpin.
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
TheIDT71V35761/781SRAMsutilizeIDT’slatesthigh-performance
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
grid array
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and 165 fine pitch ball grid array.
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0
, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
BWE
BW , BW
(1)
1
2
, BW
3
, BW
4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
TRST
ZZ
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
NOTE:
5301 tbl 01
1. BW3 and BW4 are not applicable for the IDT71V35781.
JUNE 2003
1
©2003IntegratedDeviceTechnology,Inc.
DSC-5301/03
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