IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18
Absolute Maximum Ratings (1)
Commercial &
Symbol
Rating
Unit
Industrial Values
(2)
V
V
V
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
NC
DDQ
A
NC
NC
10
(3,6)
2
79
78
77
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
3
4
V
VDDQ
5
VSS
76
75
74
73
VSS
(4,6)
TERM
Terminal Voltage with
Respect to GND
V
6
NC
NC
I/O8
NC
I/OP1
I/O
7
8
7
9
I/O9
72
71
70
I/O
6
(5,6)
TERM
Terminal Voltage with
Respect to GND
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
V
DDQ
VDDQ
69
68
67
66
65
64
63
62
61
60
59
I/O10
I/O
I/O
5
oC
oC
oC
oC
W
I/O11
4
Commercial
Operating Temperature
(1)
V
DD
V
SS
(1)
A(7)
V
DD
DD
V
V
V
DD
T
(1)
V
DD
SS/ZZ(3)
Industrial
Operating Temperature
-40 to +85
VSS
I/O12
I/O13
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
Te mp e rature
Under Bias
-55 to +125
TBIAS
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
58
57
56
55
0
Storage
Te mp e rature
-55 to +125
TSTG
VSS
VSS
,
54
53
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
P
T
Power Dissipation
DC Output Current
2.0
50
52
51
IOUT
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5281 drw 02a
5281 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
7. TA is the "instant on" case temperature.
100PinTQFPCapacitance(1)
119BGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
(TA = +25° C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
CIN
V
5
7
pF
CIN
V
7
7
pF
CI/O
V
pF
CI/O
V
pF
5281 tbl 07
5281 tbl 07a
165fBGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
TBD
TBD
pF
CI/O
V
pF
5281 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
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