IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
B
C
D
E
F
NC(3)
ADV/LD
2
3
A
9
NC
NC
CE
NC
NC
2
CE
7
2
A
DD
12
15
A
A
V
A
16
I/O
P3
I/O
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
SS
SS
13
I/O
14
I/O
1
CE
DDQ
19
I/O
12
I/O
DDQ
V
V
V
V
V
V
OE
20
I/O
21
I/O
11
I/O
10
I/O
NC(3)
G
H
J
2
BW3
BW
22
I/O
23
I/O
SS
SS
9
I/O
8
I/O
V
V
V
V
R/W
DDQ
24
DD
DD
V
DD
V
DDQ
DD(2)
SS(1)
SS
V
V
26
I/O
SS
6
I/O
7
I/O
I/O
V
CLK
NC
K
L
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
1
BW
DDQ
29
28
I/O
SS
SS
SS
SS
SS
SS
3
I/O
DDQ
V
V
V
V
V
V
M
N
P
R
T
CEN
30
I/O
1
A
2
I/O
1
I/O
I/O
31
I/O
P4
I/O
0
A
P1
I/O
0
I/O
5
DD
VSS(1)
14
13
NC
NC
DDQ
A
NC
V
A
A
NC
LBO
(6)
10
11
A
A
NC
NC/ZZ
,
(4)
(4)
(4)
(4)
(4,5)
DDQ
V
NC/TDI
NC/TCK
V
NC/TMS
U
NC/
TRST
NC/TDO
5282 drw 13A
Top View
Pin Configuration - 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(3)
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
ADV/
LD
7
A
DD
13
17
A
V
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
V
V
V
V
9
7
I/O
NC
DDQ
I/O
NC
1
CE
NC
6
I/O
DDQ
V
V
OE
10
5
I/O
NC
I/O
NC
NC
G
H
J
NC(3)
BW2
11
I/O
SS
V
SS
4
I/O
V
NC
R/W
DD(2)
SS(1)
DDQ
DD
DD
V
DD
DDQ
V
V
V
V
V
V
V
V
12
SS
SS
3
I/O
NC
I/O
NC
CLK
NC
NC
K
L
13
I/O
SS
2
I/O
V
V
V
V
NC
1
BW
DDQ
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
V
V
V
V
NC
M
N
P
R
T
CEN
15
I/O
1
A
1
I/O
NC
NC
P2
I/O
0
A
0
I/O
NC
NC
NC
DDQ
NC
5
A
DD
12
11
V
VSS(1)
14
A
NC
LBO
(6)
10
15
NC/ZZ
A
A
NC
A
A
,
(4)
(4)
(4)
(4,5)
(4)
DDQ
V
NC/TDI
NC/TCK
NC/TDO
NC/TRST
V
NC/TMS
U
5282 drw 13B
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. G4 and A4 are reserved for future 8M and 16M respectively.
4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.
6. Pin T7 supports ZZ (sleep mode) for the latest die revisions.
6.42
7