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71V321L25JG8 PDF预览

71V321L25JG8

更新时间: 2024-01-23 04:18:37
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 124K
描述
HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

71V321L25JG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:PLCC
包装说明:QCCJ, LDCC52,.8SQ针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.17
Samacsys Description:PLCC最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J52
JESD-609代码:e3长度:19.1262 mm
内存密度:16384 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端口数量:2
端子数量:52字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC52,.8SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:4.572 mm
最大待机电流:0.0015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.1 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:19.1262 mm
Base Number Matches:1

71V321L25JG8 数据手册

 浏览型号71V321L25JG8的Datasheet PDF文件第2页浏览型号71V321L25JG8的Datasheet PDF文件第3页浏览型号71V321L25JG8的Datasheet PDF文件第4页浏览型号71V321L25JG8的Datasheet PDF文件第5页浏览型号71V321L25JG8的Datasheet PDF文件第6页浏览型号71V321L25JG8的Datasheet PDF文件第7页 
HIGH SPEED 3.3V  
2K X 8 DUAL-PORT  
STATIC RAM WITH  
INTERRUPTS  
IDT71V321S/L  
Features  
High-speed access  
On-chip port arbitration logic (IDT71V321 only)  
BUSY output flag  
– Commercial & Industrial: 25/35/55ns (max.)  
Low-power operation  
– IDT71V321S  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
– IDT71V321L  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Fully asynchronous operation from either port  
Battery backup operation—2V data retention (L only)  
TTL-compatible, single 3.3V power supply  
Available in 52-pin PLCC, 64-pin TQFP and STQFP  
packages  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Two INT flags for port-to-port communications  
FunctionalBlockDiagram  
OE  
R
R
OE  
L
CE  
CEL  
R/WR  
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
(1,2)  
BUSYR  
BUSY  
L
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
R
L
R
L
(2)  
INTR  
(2)  
L
INT  
3026 drw 01  
NOTES:  
1. IDT71V321(MASTER):BUSYisanoutput  
2. BUSYandINTaretotem-poleoutputs.  
OCTOBER 2015  
1
DSC-3026/12  
©2015 Integrated Device Technology, Inc.  

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