Datasheet > 71V2558XS100PFG8

71V2558XS100PFG8

更新时间： 2023-02-26 13:45:54

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	567K
描述
ZBT SRAM, 256KX18, 5ns, CMOS, PQFP100

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数据手册

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71V2558XS100PFG8 数据手册

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs

with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

FunctionalBlockDiagram

256x18 BIT

MEMORY ARRAY

LBO

Address A [0:17]

Address

CE1, CE2, CE2

R/W

CEN

Control

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Output Register

Clock

Gate

4875 drw 01b

TMS

TDI

TCK

Data I/O [0:15],

I/O P[1:2]

JTAG

(SA Version)

TDO

TRST

(optional)

RecommendedDCOperating

Conditions

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Supply Voltage

Min.

3.135

2.375

Typ.

Max.

3.465

2.625

Unit

DDQ

3.3

2.5

____

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

1.7

DD +0.3

(2)

____

1.7

VDDQ +0.3

-0.3⁽¹⁾

0.7

4875 tbl 03

NOTES:

1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.

2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.

6.442

1 2 345 6 7...28

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