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71M6543F PDF预览

71M6543F

更新时间: 2024-02-27 06:52:42
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
157页 2164K
描述
Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation

71M6543F 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFP包装说明:LFQFP, QFP100,.63SQ,20
针数:100Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.6模拟集成电路 - 其他类型:ANALOG CIRCUIT
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Other Analog ICs最大供电电流 (Isup):8.7 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

71M6543F 数据手册

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71M6543F/H and 71M6543G/GH Data Sheet  
Figures  
Figure 1: IC Functional Block Diagram.....................................................................................................9  
Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ......................................................12  
Figure 3. AFE Block Diagram (Four CTs)...............................................................................................13  
Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) ..................................................................17  
Figure 5: States in a Multiplexer Frame (MUX_DIV[3:0] = 7) ..................................................................17  
Figure 6: General Topology of a Chopped Amplifier...............................................................................21  
Figure 7: CROSS Signal with CHOP_E = 00...........................................................................................21  
Figure 8: RTM Timing............................................................................................................................26  
Figure 9. Pulse Generator FIFO Timing .................................................................................................28  
Figure 10: Samples from Multiplexer Cycle (Frame)...............................................................................29  
Figure 11: Accumulation Interval............................................................................................................29  
Figure 12: Interrupt Structure.................................................................................................................46  
Figure 13: Automatic Temperature Compensation .................................................................................54  
Figure 14: Optical Interface....................................................................................................................58  
Figure 15: Optical Interface (UART1).....................................................................................................58  
Figure 16: Connecting an External Load to DIO Pins .............................................................................60  
Figure 17: LCD Waveforms ...................................................................................................................65  
Figure 18: 3-wire Interface. Write Command, HiZ=0..............................................................................67  
Figure 19: 3-wire Interface. Write Command, HiZ=1..............................................................................68  
Figure 20: 3-wire Interface. Read Command.........................................................................................68  
Figure 21: 3-Wire Interface. Write Command when CNT=0...................................................................68  
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1..................................................68  
Figure 23: SPI Slave Port - Typical Multi-Byte Read and Write operations..............................................70  
Figure 24: Voltage, Current, Momentary and Accumulated Energy.........................................................75  
Figure 25: Operation Modes State Diagram ...........................................................................................76  
Figure 26: MPU/CE Data Flow...............................................................................................................85  
Figure 27: Resistive Voltage Divider (Voltage Sensing)..........................................................................86  
Figure 28. CT with Single-Ended Input Connection (Current Sensing)....................................................86  
Figure 29: CT with Differential Input Connection (Current Sensing)........................................................86  
Figure 30: Differential Resistive Shunt Connections (Current Sensing)...................................................86  
Figure 31: System Using Three-Remotes and One-Local (Neutral) Sensor ............................................87  
Figure 32. System Using Current Transformers .....................................................................................88  
Figure 33: I2C EEPROM Connection......................................................................................................94  
Figure 34: Connections for UART0 ........................................................................................................94  
Figure 35: Connection for Optical Components......................................................................................95  
Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) .......96  
Figure 37: External Components for the Emulator Interface ...................................................................96  
Figure 38. Trim Fuse Bit Mapping........................................................................................................118  
Figure 39: CE Data Flow: Multiplexer and ADC....................................................................................131  
Figure 40: CE Data Flow: Scaling, Gain Control, Intermediate Variables for one Phase........................131  
Figure 41: CE Data Flow: Squaring and Summation Stages.................................................................132  
Figure 42: Wh Error from 200 A to 0.1 A at 60 Hz, 240 VAC ......................Error! Bookmark not defined.  
Figure 43: VARh Error from 200 A to 0.1 A at 60 Hz, 240 VAC...................Error! Bookmark not defined.  
Figure 44: Wh Error from 200 A to 0.1 A at Various Frequencies (0° Load angle, 240 VAC)............. Error!  
Bookmark not defined.  
Figure 45: 100-pin LQFP Package Outline...........................................................................................148  
Figure 46: Pinout for the LQFP-100 Package.......................................................................................149  
Figure 47: I/O Equivalent Circuits.........................................................................................................154  
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