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7164L15YG PDF预览

7164L15YG

更新时间: 2024-01-19 02:37:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
11页 133K
描述
Standard SRAM, 8KX8, 15ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, SOJ-28

7164L15YG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOJ包装说明:0.300 INCH, ROHS COMPLIANT, SOJ-28
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.62最长访问时间:15 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J28
JESD-609代码:e3内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ28,.34封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大待机电流:0.00006 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.15 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
Base Number Matches:1

7164L15YG 数据手册

 浏览型号7164L15YG的Datasheet PDF文件第2页浏览型号7164L15YG的Datasheet PDF文件第3页浏览型号7164L15YG的Datasheet PDF文件第4页浏览型号7164L15YG的Datasheet PDF文件第6页浏览型号7164L15YG的Datasheet PDF文件第7页浏览型号7164L15YG的Datasheet PDF文件第8页 
IDT7164S/L  
CMOS Static RAM 64K (8K x 8-Bit)  
Military, Commercial, and Industrial Temperature Ranges  
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)  
7164S15(1)  
7164L15(1)  
7164S20(2)  
7164L20(2)  
7164S25  
7164S35  
7164L35  
7164L25  
Symbol  
Parameter  
Unit  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Read Cycle  
____  
____  
____  
____  
t
RC  
Read Cycle Time  
15  
20  
25  
35  
ns  
ns  
ns  
____  
____  
____  
____  
tAA  
Address Access Time  
15  
15  
19  
20  
25  
25  
35  
35  
____  
____  
____  
____  
____  
____  
____  
____  
(3)  
ACS1  
Chip Select-1 Access Time  
t
(3)  
ACS2  
Chip Select-2 Access Time  
20  
25  
30  
40  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
(4)  
CLZ1,2  
____  
____  
____  
____  
Chip Select-1, 2 to Output in Low-Z  
Output Enable to Output Valid  
Output Enable to Output in Low-Z  
Chip Select-1,2 to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
Chip Select to Power Up Time  
Chip Deselect to Power Down Time  
5
5
5
5
t
____  
____  
____  
____  
tOE  
7
8
12  
18  
____  
____  
____  
____  
(4)  
OLZ  
0
0
0
0
t
____  
____  
____  
____  
(4)  
CHZ1,2  
8
9
13  
15  
t
____  
____  
____  
____  
(4)  
OHZ  
7
8
10  
15  
t
____  
____  
____  
____  
tOH  
5
5
5
5
____  
____  
____  
____  
(4)  
PU  
0
0
0
0
t
____  
____  
____  
____  
(4)  
PD  
15  
20  
25  
35  
t
Write Cycle  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
WC  
CW1,2  
AW  
AS  
WP  
WR1  
WR2  
Write Cycle Time  
15  
14  
14  
0
20  
15  
15  
0
25  
18  
18  
0
35  
25  
25  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Chip Select to End-of-Write  
Address Valid to End-of-Write  
Address Set-up Time  
Write Pulse Width  
t
t
t
14  
0
15  
0
21  
0
25  
0
t
Write Recovery Time (CS  
1
, WE)  
t
Write Recovery Time (CS  
2)  
5
5
5
5
____  
____  
____  
____  
(4)  
WHZ  
Write Enable to Output in High-Z  
Data to Write Time Overlap  
6
8
10  
14  
t
____  
____  
____  
____  
t
DW  
DH1  
DH2  
8
0
5
4
10  
0
13  
0
15  
0
____  
____  
____  
____  
____  
____  
____  
____  
t
Data Hold from Write Time (CS , WE)  
1
t
Data Hold from Write Time (CS  
2)  
5
5
5
____  
____  
____  
____  
(4)  
OW  
Output Active from End-of-Write  
4
4
4
ns  
t
2967 tbl 12  
NOTES:  
1. 0° to +70°C temperature range only.  
2. 0° to +70°C and –55°C to +125°C temperature ranges only.  
3. Both chip selects must be active for the device to be selected.  
4. This parameter is guaranteed by device characterization, but is not production tested.  
6.42  
5

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