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71421SA55JG8 PDF预览

71421SA55JG8

更新时间: 2024-09-29 20:03:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 161K
描述
Dual-Port SRAM, 2KX8, 55ns, CMOS, PQCC52, PLASTIC, LCC-52

71421SA55JG8 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, LDCC52,.8SQ针数:52
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.14
Is Samacsys:N最长访问时间:55 ns
其他特性:INTERRUPT FLAG; AUTOMATIC POWER-DOWNI/O 类型:COMMON
JESD-30 代码:S-PQCC-J52JESD-609代码:e3
长度:19.1262 mm内存密度:16384 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端口数量:2端子数量:52
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC52,.8SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:4.572 mm最大待机电流:0.015 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.155 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:19.1262 mmBase Number Matches:1

71421SA55JG8 数据手册

 浏览型号71421SA55JG8的Datasheet PDF文件第2页浏览型号71421SA55JG8的Datasheet PDF文件第3页浏览型号71421SA55JG8的Datasheet PDF文件第4页浏览型号71421SA55JG8的Datasheet PDF文件第5页浏览型号71421SA55JG8的Datasheet PDF文件第6页浏览型号71421SA55JG8的Datasheet PDF文件第7页 
IDT71321SA/LA  
IDT71421SA/LA  
HIGH SPEED  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
Features  
MASTER IDT71321 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT71421  
High-speed access  
– Commercial: 20/25/35/55ns (max.)  
Industrial: 55ns (max.)  
Low-power operation  
On-chip port arbitration logic (IDT71321 only)  
BUSY output flag on IDT71321; BUSY input on IDT71421  
Fully asynchronous operation from either port  
Battery backup operation – 2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
IDT71321/IDT71421SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71321/421LA  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Two INT flags for port-to-port communications  
FunctionalBlockDiagram  
OER  
OEL  
CEL  
R/WL  
CER  
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
A10L  
A0L  
A10R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0R  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CEL  
OEL  
CER  
OER  
R/WR  
R/WL  
(2)  
INTR  
(2)  
INTL  
2691 drw 01  
NOTES:  
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270.  
IDT71421 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
MARCH 1999  
1
DSC-2691/8  
©1999IntegratedDeviceTechnology,Inc.  
1

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