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7133LA45JB PDF预览

7133LA45JB

更新时间: 2024-02-29 17:31:44
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
16页 137K
描述
Dual-Port SRAM, 2KX16, 45ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

7133LA45JB 数据手册

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IDT7133SA/LA,IDT7143SA/LA  
High-Speed 2K x 16 Dual-Port RAM  
Military, Industrial and Commercial Temperature Ranges  
RAM or as a MASTER” Dual-Port RAM together with the IDT7143 port to enter a very low standby power mode.  
SLAVE”Dual-Portin32-bit-or-morewordwidthsystems.UsingtheIDT  
FabricatedusingIDT’s CMOShigh-performance technology, these  
MASTER/SLAVEDual-PortRAMapproachin32-bit-or-widermemory devices typically operate on only 1,150mW of power. Low-power (LA)  
systemapplicationsresultsinfull-speed,error-freeoperationwithoutthe versions offer battery backup data retention capability, with each port  
needforadditionaldiscretelogic.  
typicallyconsuming200µWfora2Vbattery.  
Both devices provide two independent ports with separate control,  
The IDT7133/7143 devices have identical pinouts. Each is packed  
address, and I/O pins that permit independent, asynchronous access in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin  
for reads or writes to any location in memory. An automatic power TQFP. Military grade product is manufactured in compliance with the  
down feature, controlled by CE, permits the on-chip circuitry of each latest revision of MIL-PRF-38535 QML, making it ideally suited to  
military temperature applications demanding the highest level of  
performance and reliability.  
Pin Configurations(1,2,3)  
INDEX  
9
8
7
6
5
4
3
2
68 67 66 65 64 63 62 61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
I/O9L  
I/O10L  
I/O11L  
I/O12L  
I/O13L  
I/O14L  
I/O15L  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
A
A
A
A
A
A
A
6L  
5L  
4L  
3L  
2L  
1L  
0L  
1
IDT7133/43  
J68-1 / F68-1(4)  
V
CC(1)  
BUSY  
CE  
CE  
BUSY  
L
(2)  
GND  
I/O0R  
I/O1R  
I/O2R  
I/O3R  
I/O4R  
I/O5R  
I/O6R  
I/O7R  
L
68-Pin PLCC/Flatpack  
(5)  
R
Top View  
R
A0R  
A1R  
A2R  
A3R  
A4R  
A5R  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
,
2746 drw 02  
Index  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  
N/C  
N/C  
N/C  
1
N/C  
N/C  
N/C  
N/C  
75  
2
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
3
N/C  
4
A
A
A
A
A
A
5L  
4L  
3L  
2L  
1L  
0L  
I/O10L  
I/O11L  
I/O12L  
I/O13L  
GND  
5
6
7
8
9
IDT7133/43PF  
PN100-1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
I/O14L  
I/O15L  
(4)  
N/C  
BUSY  
GND  
L
VCC  
100-Pin TQFP  
GND  
I/O0R  
I/O1R  
I/O2R  
(5)  
Top View  
N/C  
BUSY  
N/C  
R
A
A
A
A
A
0R  
1R  
2R  
3R  
4R  
VCC  
I/O3R  
I/O4R  
I/O5R  
I/O6R  
N/C  
N/C  
N/C  
N/C  
NOTES:  
1. Both VCC pins must be connected to the power supply to ensure reliable  
operation.  
2. Both GND pins must be connected to the ground supply to ensure reliable  
operation.  
N/C  
N/C  
N/C  
N/C  
3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in.  
F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in.  
PN100-Package body is approximately 14mm x 14mm x 1.4mm.  
4. This package code is used to reference the package diagram.  
5. This text does not indicate orientation of the actual part-marking.  
,
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
2746 drw 03  
6.42  
2

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