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70V5378S100BCGI8 PDF预览

70V5378S100BCGI8

更新时间: 2024-01-20 17:58:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
29页 247K
描述
Multi-Port SRAM, 32KX18, 3.6ns, CMOS, PBGA256

70V5378S100BCGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:BGA, BGA256,16X16,40
Reach Compliance Code:compliant风险等级:5.84
Base Number Matches:1

70V5378S100BCGI8 数据手册

 浏览型号70V5378S100BCGI8的Datasheet PDF文件第2页浏览型号70V5378S100BCGI8的Datasheet PDF文件第3页浏览型号70V5378S100BCGI8的Datasheet PDF文件第4页浏览型号70V5378S100BCGI8的Datasheet PDF文件第5页浏览型号70V5378S100BCGI8的Datasheet PDF文件第6页浏览型号70V5378S100BCGI8的Datasheet PDF文件第7页 
3.3V 64/32K X 18  
SYNCHRONOUS  
IDT70V5388/78  
FOURPORT™ STATIC RAM  
Features  
Counter wrap-around control  
Internal mask register controls counter wrap-around  
– Counter-Interrupt flags to indicate wrap-around  
Mask register readback on address lines  
Global Master reset for all ports  
Dual Chip Enables on all ports for easy depth expansion  
Separate upper-word and lower-word controls on all ports  
272-BGA package (27mm x 27mm 1.27mm ball pitch) and  
256-BGA package (17mm x 17mm 1.0mm ball pitch)  
Commercial and Industrial temperature ranges  
JTAG boundary scan  
True four-ported memory cells which allow simultaneous  
access of the same memory location  
Synchronous Pipelined device  
– 64/32K x 18 organization  
Pipelined output mode allows fast 200MHz operation  
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x  
4 ports)  
LVTTL I/O interface  
High-speed clock to data access 3.0ns (max.)  
3.3V Low operating power  
Interrupt flags for message passing  
Width and depth expansion capabilities  
Counter readback on address lines  
MBIST (Memory Built-In Self Test) controller  
Green parts available, see ordering information  
Port - 1 Logic Block Diagram(2)  
R/  
W
P1  
0
1
1/0  
U B P1  
C E 0P1  
CE1P1  
L B P1  
O E P1  
I/O9P1 - I/O17P1  
I/O0P1 - I/O8P1  
Port 1  
I/O  
Control  
TR S T  
TMS  
JTAG  
TCK  
TDI  
Controller  
MBIST  
TDO  
CLKMBIST  
Addr.  
Read  
Back  
Port 1  
Readback  
Register  
M R S T  
(1)  
A
0P1 - A15P1  
Port 1  
Mask  
,
Register  
C N TR D P1  
M K R D P1  
M K L D P1  
Port 1  
Address  
Decode  
64KX18  
Memory  
Array  
Priority  
Decision  
Logic  
Port 1  
C N TIN C P1  
C N TL D P1  
C N TR S TP1  
Counter/  
Address  
Register  
CLKP1  
R/  
W P1  
Port 1  
Interrupt  
Logic  
C E 0P1  
CE1P1  
CLKP1  
M R S T  
C N TIN T P1  
IN TP1  
M R S T  
5649 drw 01  
NOTE:  
1. A15x is a NC for IDT70V5378.  
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.  
JANUARY 2006  
1
DSC-5649/4  
©2006IntegratedDeviceTechnology,Inc.  

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