Datasheet > 7024

7024

更新时间： 2023-12-20 18:44:44

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
23页	336K
描述
4K x 16 Dual-Port RAM

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数据手册

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7024 数据手册

7024S/L

High-Speed 4K x 16 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

ACE

(4)

tAOE

(4)

tABE

UB, LB

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

2740 drw 07

tBDD

NOTES:

1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has

no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

ICC

2740 drw 08

6.42

Feb.20.20

1...6 7 8910 11 12...23

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