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7008L55JG PDF预览

7008L55JG

更新时间: 2024-01-10 23:09:54
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
19页 155K
描述
Multi-Port SRAM, 64KX8, 55ns, CMOS, PQCC84

7008L55JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:QCCJ, LDCC84,1.2SQ
Reach Compliance Code:compliant风险等级:5.26
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J84JESD-609代码:e3
内存密度:524288 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:2
端子数量:84字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大待机电流:0.005 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.23 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

7008L55JG 数据手册

 浏览型号7008L55JG的Datasheet PDF文件第2页浏览型号7008L55JG的Datasheet PDF文件第3页浏览型号7008L55JG的Datasheet PDF文件第4页浏览型号7008L55JG的Datasheet PDF文件第5页浏览型号7008L55JG的Datasheet PDF文件第6页浏览型号7008L55JG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7008S/L  
64K x 8 DUAL-PORT  
STATIC RAM  
Features  
IDT7008 easily expands data bus width to 16 bits or  
more using the Master/Slave select when cascading more  
than one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:15/20/25/35/55ns(max.)  
Industrial:20/55ns (max.)  
Military:25/35/55ns(max.)  
Low-power operation  
IDT7008S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
IDT7008L  
Active:750mW(typ.)  
Standby: 1mW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
Green parts available, see ordering information  
FunctionalBlockDiagram  
L
R/W  
R
R/W  
CE0L  
CE1L  
CE0R  
CE  
1
R
OEL  
OER  
I/O  
Control  
I/O  
Control  
I/O0-7L  
I/O0-7R  
(1,2)  
BUSYL  
(1,2)  
BUSYR  
64Kx8  
MEMORY  
ARRAY  
7008  
15R  
A
15L  
A
Address  
Decoder  
Address  
Decoder  
0R  
A
A
0L  
16  
16  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0L  
CE0R  
1L  
CE  
1R  
CE  
L
L
OE  
R/W  
OER  
R
R/W  
SEM  
INTL  
L
R
SEM  
(2)  
(2)  
R
INT  
M/S(1)  
3198 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
APRIL 2006  
1
DSC 3198/8  
©2006IntegratedDeviceTechnology,Inc.  

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