Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
November 5, 1998
TABLE OF CONTENTS
Section
Page
4.5
HARDWARE INTERRUPTS ............................................................................ 4-4
External Interrupt IRQ.................................................................................. 4-4
IRQ Control/Status Register (ICSR) - $0A................................................... 4-5
Port A External Interrupts (PA0-PA3, by mask option)................................ 4-6
Timer1 Interrupt (TIMER1)........................................................................... 4-7
USB Interrupt (USB) .................................................................................... 4-7
MFT Interrupt (MFT) .................................................................................... 4-7
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
SECTION 5
RESETS
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
POWER-ON RESET........................................................................................ 5-2
EXTERNAL RESET ......................................................................................... 5-2
INTERNAL RESETS........................................................................................ 5-2
Power-On Reset (POR)............................................................................... 5-2
USB Reset................................................................................................... 5-3
Computer Operating Properly (COP) Reset ................................................ 5-3
Low Voltage Reset (LVR) ............................................................................ 5-3
Illegal Address Reset................................................................................... 5-4
SECTION 6
LOW POWER MODES
6.1
6.2
6.3
STOP MODE.................................................................................................... 6-3
WAIT MODE .................................................................................................... 6-3
DATA-RETENTION MODE.............................................................................. 6-3
SECTION 7
INPUT/OUTPUT PORTS
7.1
PORT-A............................................................................................................ 7-1
Port-A Data Register.................................................................................... 7-2
Port-A Data Direction Register .................................................................... 7-2
Port-A Pull-down/up Register ...................................................................... 7-2
PA0-PA3 Interrupts...................................................................................... 7-2
PA0-PA7 Optical Interface........................................................................... 7-3
PORT-B............................................................................................................ 7-3
Port-B Data Register.................................................................................... 7-3
Port-B Data Direction Register .................................................................... 7-3
Port-B Pull-down/up Register ...................................................................... 7-4
PB1, PB2 Slow Transition Output................................................................ 7-4
PORT-C ........................................................................................................... 7-5
Port-C Data Register ................................................................................... 7-5
Port-C Data Direction Register .................................................................... 7-5
Port-C Pull-down/up Register ...................................................................... 7-6
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
MOTOROLA
ii
MC68HC05JB3
REV 1
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