Datasheet > 68HC05C5

68HC05C5

更新时间： 2022-12-16 12:55:43

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
58页	1419K
描述
SPECIFICATION (General Release)

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68HC05C5 数据手册

Freescale Semiconductor, Inc.

MC68HC05C5 Specification Rev. 1.2

LIST OF FIGURES

Figure 1-1:

Self-Check Mode Schematic for the MC68HC05C5.................................2

Figure 2-1:

Figure 2-2:

Single-Chip Mode Pinout of the MC68HC05C5........................................6

Self-Check Mode Schematic for the MC68HC05C5.................................7

Figure 3-1:

Figure 3-2:

Figure 3-3:

The 8K Memory Map of the MC68HC05C5..............................................9

I/O Registers for the MC68HC05C5 .......................................................10

Programming Register............................................................................11

Figure 4-1:

Figure 4-2:

Figure 4-3:

Figure 4-4:

Figure 4-5:

Figure 4-6:

Programming Model ...............................................................................15

Stacking Order........................................................................................15

Power-On Reset and RESET .................................................................23

Interrupt Flowchart..................................................................................27

Stop Recovery Timing Diagram..............................................................28

STOP/WAIT Flowcharts..........................................................................29

Figure 5-1:

Port I/O Circuitry .....................................................................................32

Figure 6-1:

Figure 6-2:

Figure 6-3:

Timer Block Diagram ..............................................................................33

Timer Control Register............................................................................35

Timer Status Register.............................................................................37

Figure 7-1:

Figure 7-2:

Figure 7-3:

Figure 7-4:

Figure 7-5:

Figure 7-6:

SIOP Block Diagram...............................................................................39

Serial I/O Port Timing (CPOL=1) ............................................................40

Serial I/O Port Timing (CPOL=0) ............................................................40

SIOP Control Register ............................................................................40

SIOP Status Register..............................................................................42

SIOP Data Register ................................................................................42

Figure 9-1:

Figure 9-2:

Figure 9-3:

Stop Recovery Timing Diagram..............................................................48

LVPI Timing Diagram..............................................................................48

SIOP Timing Diagram.............................................................................49

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