IDT5V41066
4 OUTPUT PCIE GEN1/2 SYNTHESIZER
Application Information
Decoupling Capacitors
Load Resistors RL
As with any high-performance mixed-signal IC, the
IDT5V41066 must be isolated from system power supply
noise to perform optimally.
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41066 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
The IDT5V41066 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41066.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pairs (1,9 and 15,16)
as close to the device as possible.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C -12)*2 in this equation, C =crystal
L
L
load capacitance in pf. For example, for a crystal with a 16
pF load cap, each external crystal cap would be 8 pF.
[(16-12)x2]=8.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (I ) is
OH
equal to 6*IREF.
IDT® 4 OUTPUT PCIE GEN1/2 SYNTHESIZER
4
IDT5V41066 REV D 112211
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