IDT5T995/A
INDUSTRIALTEMPERATURERANGE
2.5VPROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCKII
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
5T995
5T995A
Typ.
Symbol
FNOM
tRPWH
tRPWL
tU
Parameter
Min.
Typ.
Max.
Min.
Max.
Unit
VCO Frequency Range
REF Pulse Width HIGH(1)
REF Pulse Width LOW(1)
SeeProgrammableSkewRangeandResolutionTable
2
2
—
—
—
—
2
2
—
—
—
—
ns
ns
ProgrammableSkewTimeUnit
SeeControlSummaryTable
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3)
ZeroOutputSkew(AllOutputs)(4)
—
—
50
0.1
0.1
0.2
0.15
0.3
—
185
0.25
0.25
0.5
0.5
0.9
0.75
0.3
0.5
0.7
0.7
1
—
—
50
0.1
0.1
0.2
0.15
0.3
—
185
0.25
0.25
0.5
0.5
0.9
0.75
0.25
0.25
0.5
0.7
1
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5)
OutputSkew(Rise-Fall,Nominal-Inverted,Divided-Divided)(5)
OutputSkew(Rise-Rise,Fall-Fall,DifferentClassOutputs)(5)
OutputSkew(Rise-Fall,Nominal-Divided,Divided-Inverted)(2)
Device-to-Device Skew(2,6)
Static Phase Offset (FS = L, M, H) (FB Divide-by-n = 1, 2, 3)(7)
Static Phase Offset (FS = H)(7)
Static Phase Offset (FS = M)(7)
Static Phase Offset (FS = L) (FB Divide-by-n = 1, 2, 3, 4, 5, 6)(7)
Static Phase Offset (FS = L) (FB Divide-by-n = 8, 10, 12)(7)
Output Duty Cycle Variation from 50%
Output HIGH Time Deviation from 50%(8)
OutputLOWTimeDeviationfrom50%(9)
OutputRiseTime
—
—
—
—
—
—
—
—
—
—
t(φ)1-3
−0.3
−0.5
−0.7
−0.7
−1
−1
—
—
−0.25
−0.25
−0.5
−0.7
−1
−1
—
—
t(φ)H
—
—
t(φ)M
—
—
t(φ)L1-6
t(φ)L8-12
tODCV
tPWH
—
—
—
—
—
1
—
1
—
1.5
2
—
1.5
2
tPWL
—
—
—
—
tORISE
tOFALL
tLOCK
tCCJH
0.15
0.15
—
0.7
0.7
—
1.5
1.5
0.5
100
0.15
0.15
—
0.7
0.7
—
1.5
1.5
0.5
100
OutputFallTime
PLLLockTime(10,11)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=1,2)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = H, FB divide-by-n=any)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = M)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = L, FREF > 3MHz)
Cycle-to-CycleOutputJitter(peak-to-peak)
(divide by 1 output frequency, FS = L, FREF < 3MHz)
—
—
—
—
tCCJHA
tCCJM
tCCJL
—
—
—
—
—
—
—
—
150
200
200
300
—
—
—
—
—
—
—
—
150
150
200
300
ps
tCCJLA
NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified
load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSK(0) is the skew between outputs when they are selected for 0tU.
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-
by-4 mode). Test condition: nF0:1=MM is set on unused outputs.
6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)
7. tφ is measured with REF input rise and fall times (from 0.7V to 1.7V) of 0.5ns. Measured from 1.25V on REF to 1.25V on FB.
8. Measured at 1.7V.
9. Measured at 0.7V.
10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
11. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.
7
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