Datasheet > 5P35023-dddNLGI8

5P35023-dddNLGI8

更新时间： 2024-01-27 04:07:24

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
34页	385K
描述
Programmable Clock Generator

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中文翻译

获取价格

数据手册

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5P35023-dddNLGI8 数据手册

5P35023 DATASHEET

Functional Block Diagram

DIV1/REF

DIV3

VDDDIFF2

OSC

DIFF2

DIFF2B

MUX

DIV1

DIV2

MUX

CLKINB/X1

VDDDIFF1

PLL1

PLL2

DIV1/REF

DIV3

CLKIN/X2

DIFF1

DIFF1B

DIV2

OE3

Power

VBAT

DIV3

DIV4

MUX

DIV4/REF

32K

MUX

SE3

VDDSE3

Monitor

VDD33

POR

DIV4/REF

DIV5

OE2

SE2

VDDSE2

32K

VDDA

MUX

DIV5

PLL3

DIV4/REF

DIV5

OE1

SE1

Calibriation

VSS

32K

VDDSE1

32.768K

DCO

REF

SCL_DFC1

I2C Engine

SDA_DFC0

Overshot Reduction

(ORT)

Dynamic Frequency Control Logic (DFC)

OTP memory (1 configuration)

Proactive Power Saving Logic (PPS)

Timer

Power Group

Power supply table

DIFF

DIV

MUX

PLL

DCO

REF

Xtal

SE1

SE2*

SE3*

VDDSE1

VDDSE2

VDDSE3

VDDDIFF1

VDDDIFF2

VDD33

DIFF1

DIFF2

DIV3/4

DIV1

MUXPLL2 PLL2

MUXPLL1

DIV5

PLL3

DCO

REF

Xtal

VBAT

DIV2

PLL1

VDDA

* VDDSEx for non 32KHz outputs shoue be OFF when VDDA/VDD3 turn OFF, VBAT mode only support

32.768KHz outputs from SE1~3

* SE2 & SE3 only available in 5P35023

* Vbat power ramp up should be same or earlier than other Vdd power rail

Output Source Table

Outputs

Source

REF

SE1

SE2*

SE3*

Xtal REF

32.768KHz

PLL1

DIFF1

DIFF2

Xtal REF

32.768KHz

Xtal REF

32.768KHz

Xtal REF

32.768KHz

PLL1

PLL2

PLL3

PLL1

PLL2

PLL3

PLL2

PLL3

PLL2

PLL3

PLL2

PLL3

* SE2 & SE3 only available in 5P35023

VERSACLOCK^®PROGRAMMABLE CLOCK GENERATOR

JANUARY 25, 2017

123 4 5 6 7...34

中文翻译

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