Datasheet > 5M1270ZT144A5N

5M1270ZT144A5N

更新时间： 2024-02-23 20:11:55

品牌	Logo	应用领域
阿尔特拉 - ALTERA		开关
页数	文件大小	规格书
30页	489K
描述
3. DC and Switching Characteristics for MAX V Devices

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5M1270ZT144A5N 技术参数

3–30

Chapter 3: DC and Switching Characteristics for MAX V Devices

Document Revision History

Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 2 of 2)

Symbol

Parameter

Min

Max

Unit

t_JSXZ

Notes to Table 3–41:

(1) Minimum clock period specified for 10 pF load on the TDOpin. Larger loads on TDOdegrades the maximum TCKfrequency.

Update register valid output to high impedance

—

(2) This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For 1.8-V LVTTL/LVCMOS and

1.5-V LVCMOS operation, the t_JPSUminimum is 6 ns and t_JPCO, t_JPZX, and t_JPXZare maximum values at 35 ns.

Document Revision History

Table 3–42 lists the revision history for this chapter.

Table 3–42. Document Revision History

Date

May 2011

Version

1.2

Changes

Updated Table 3–2, Table 3–15, Table 3–16, and Table 3–33.

Updated Table 3–37, Table 3–38, Table 3–39, and Table 3–40.

Initial release.

January 2011

1.1

December 2010

1.0

MAX V Device Handbook

May 2011 Altera Corporation

1...27 28 2930

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型号	品牌	描述	获取价格	数据表
5M1270ZT144C4N	INTEL	Flash PLD, 8.1ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144	获取价格
5M1270ZT144C5N	ALTERA	DC and Switching Characteristics for MAX V Devices	获取价格
5M1270ZT144C5N	INTEL	Flash PLD, 10ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144	获取价格
5M1270ZT144I5N	ALTERA	Flash PLD, 10ns, 980-Cell, CMOS, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144	获取价格
5M1270ZT64A4N	ALTERA	MAX V Device Handbook	获取价格
5M1270ZT64A5N	ALTERA	MAX V Device Handbook	获取价格