Datasheet > 5CSXFC6D6U23C8N

5CSXFC6D6U23C8N

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
64页	1355K
描述
Field Programmable Gate Array, PBGA672, ROHS COMPLIANT, UBGA-672

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5CSXFC6D6U23C8N 数据手册

Electrical Characteristics

Page 7

I/O Pin Leakage Current

Table 6 lists the Cyclone V I/O pin leakage current specifications.

Table 6. I/O Pin Leakage Current for Cyclone V Devices

Symbol

I_I

I_OZ

Description

Input pin

Tri-stated I/O pin

Conditions

V_I= 0 V to V_CCIOMAX

V_O= 0 V to V_CCIOMAX

Min

–30

Typ

—

Max

Unit

µA

—

µA

Bus Hold Specifications

Table 7 lists the Cyclone V device bus hold specifications. The bus-hold trip points are

based on calculated input voltages from the JEDEC standard.

Table 7. Bus Hold Parameters for Cyclone V Devices

V_CCIO(V)

Parameter Symbol Conditions

1.2

1.5

1.8

2.5

3.0

3.3

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Bus-hold,

low,

sustaining

current

V_IN> V_IL

(max.)

I_SUSL

I_SUSH

I_ODL

—

–12

—

–30

—

–50

—

–70

—

–70

—

µA

Bus-hold,

high,

sustaining

current

V_IN< V_IH

(min.)

–8

—

Bus-hold,

low,

overdrive

current

0V < V_IN

V_CCIO

125

–125

175

–175

200

–200

300

500

500 µA

–500 µA

Bus-hold,

high,

overdrive

current

0V < V_IN

V_CCIO

I_ODH

—

–300

1.7

—

–500

—

Bus-hold

trip point

V_TRIP

—

0.3

0.9 0.375 1.125 0.68 1.07 0.7

0.8

December 2013 Altera Corporation

Cyclone V Device Datasheet

1...4 5 678 9 10...64

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