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5CSXFC5D6F31C7N PDF预览

5CSXFC5D6F31C7N

更新时间: 2024-01-19 01:43:08
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
66页 1360K
描述
Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896

5CSXFC5D6F31C7N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:BGA, BGA896,30X30,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
JESD-30 代码:S-PBGA-B896JESD-609代码:e1
长度:31 mm湿度敏感等级:3
输入次数:288逻辑单元数量:85000
输出次数:288端子数量:896
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA896,30X30,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.1,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.13 V
最小供电电压:1.07 V标称供电电压:1.1 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:31 mmBase Number Matches:1

5CSXFC5D6F31C7N 数据手册

 浏览型号5CSXFC5D6F31C7N的Datasheet PDF文件第4页浏览型号5CSXFC5D6F31C7N的Datasheet PDF文件第5页浏览型号5CSXFC5D6F31C7N的Datasheet PDF文件第6页浏览型号5CSXFC5D6F31C7N的Datasheet PDF文件第8页浏览型号5CSXFC5D6F31C7N的Datasheet PDF文件第9页浏览型号5CSXFC5D6F31C7N的Datasheet PDF文件第10页 
Electrical Characteristics  
Page 7  
The Quartus II PowerPlay Power Analyzer provides better quality estimates based on  
the specifics of the design after you complete place-and-route. The PowerPlay Power  
Analyzer can apply a combination of user-entered, simulation-derived, and estimated  
signal activities that, when combined with detailed circuit models, yields very  
accurate power estimates.  
f
For more information about power estimation tools, refer to the PowerPlay Early Power  
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II  
Handbook.  
I/O Pin Leakage Current  
Table 6 lists the Cyclone V I/O pin leakage current specifications.  
Table 6. I/O Pin Leakage Current for Cyclone V Devices  
Symbol  
II  
IOZ  
Description  
Input pin  
Tri-stated I/O pin  
Conditions  
VI = 0 V to VCCIOMAX  
VO = 0 V to VCCIOMAX  
Min  
–30  
–30  
Typ  
Max  
30  
Unit  
µA  
30  
µA  
Bus Hold Specifications  
Table 7 lists the Cyclone V device bus hold specifications. The bus-hold trip points are  
based on calculated input voltages from the JEDEC standard.  
Table 7. Bus Hold Parameters for Cyclone V Devices  
VCCIO (V)  
Parameter Symbol Conditions  
1.2  
1.5  
1.8  
2.5  
3.0  
3.3  
Unit  
Min Max Min Max Min Max Min Max Min Max Min Max  
Bus-hold,  
low,  
sustaining  
current  
VIN > VIL  
(max.)  
ISUSL  
ISUSH  
IODL  
8
12  
–12  
30  
–30  
50  
–50  
70  
–70  
70  
–70  
µA  
µA  
Bus-hold,  
high,  
sustaining  
current  
VIN < VIH  
(min.)  
–8  
Bus-hold,  
low,  
overdrive  
current  
0V < VIN  
VCCIO  
<
125  
–125  
175  
–175  
200  
–200  
300  
500  
500 µA  
–500 µA  
Bus-hold,  
high,  
overdrive  
current  
0V < VIN  
VCCIO  
<
IODH  
–300  
1.7  
–500  
2
Bus-hold  
trip point  
VTRIP  
0.3  
0.9 0.375 1.125 0.68 1.07 0.7  
0.8  
0.8  
2
V
July 2014 Altera Corporation  
Cyclone V Device Datasheet  

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