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5CEBA2F23C7N PDF预览

5CEBA2F23C7N

更新时间: 2024-02-22 11:56:52
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑
页数 文件大小 规格书
37页 353K
描述
Field Programmable Gate Array, PBGA484, ROHS COMPLIANT, FBGA-484

5CEBA2F23C7N 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:BGA包装说明:BGA,
针数:484Reach Compliance Code:compliant
风险等级:5.79JESD-30 代码:S-PBGA-B484
长度:23 mm端子数量:484
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
座面最大高度:2 mm最大供电电压:1.13 V
最小供电电压:1.07 V标称供电电压:1.1 V
表面贴装:YES温度等级:OTHER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:23 mmBase Number Matches:1

5CEBA2F23C7N 数据手册

 浏览型号5CEBA2F23C7N的Datasheet PDF文件第1页浏览型号5CEBA2F23C7N的Datasheet PDF文件第2页浏览型号5CEBA2F23C7N的Datasheet PDF文件第3页浏览型号5CEBA2F23C7N的Datasheet PDF文件第5页浏览型号5CEBA2F23C7N的Datasheet PDF文件第6页浏览型号5CEBA2F23C7N的Datasheet PDF文件第7页 
Cyclone V Device Overview  
CV-51001 | 2018.05.07  
Summary of Cyclone V Features  
Table 2.  
Summary of Features for Cyclone V Devices  
Feature  
Description  
Technology  
TSMC's 28-nm low-power (28LP) process technology  
1.1 V core voltage  
Packaging  
Wirebond low-halogen packages  
Multiple device densities with compatible package footprints for seamless migration between  
different device densities  
RoHS-compliant and leaded(1)options  
High-performance  
FPGA fabric  
Enhanced 8-input ALM with four registers  
Internal memory  
blocks  
M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)  
Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25%  
of the ALMs as MLAB memory  
Embedded Hard IP  
blocks  
Variable-precision DSP  
Native support for up to three signal processing precision levels  
(three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same  
variable-precision DSP block  
64-bit accumulator and cascade  
Embedded internal coefficient memory  
Preadder/subtractor for improved efficiency  
Memory controller  
DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support  
Embedded transceiver  
I/O  
PCI Express* (PCIe*) Gen2 and Gen1 (x1, x2, or x4) hard IP with  
multifunction support, endpoint, and root port  
Clock networks  
Up to 550 MHz global clock network  
Global, quadrant, and peripheral clock networks  
Clock networks that are not used can be powered down to reduce dynamic power  
Phase-locked loops  
(PLLs)  
Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)  
Integer mode and fractional mode  
FPGA General-purpose  
I/Os (GPIOs)  
875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter  
400 MHz/800 Mbps external memory interface  
On-chip termination (OCT)  
3.3 V support with up to 16 mA drive strength  
Low-power high-speed  
serial interface  
614 Mbps to 6.144 Gbps integrated transceiver speed  
Transmit pre-emphasis and receiver equalization  
Dynamic partial reconfiguration of individual channels  
HPS  
Single or dual-core Arm Cortex-A9 MPCore processor-up to 925 MHz maximum frequency with  
support for symmetric and asymmetric multiprocessing  
(Cyclone V SE, SX,  
and ST devices only)  
Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0  
On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND  
flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area  
network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO  
interfaces  
System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA)  
controller, FPGA configuration manager, and clock and reset managers  
On-chip RAM and boot ROM  
continued...  
(1)  
Contact Intel for availability.  
Cyclone V Device Overview  
4
 

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