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5CEBA2F23C7N

更新时间： 2024-01-18 18:52:08
品牌 Logo 应用领域
阿尔特拉 - ALTERA 栅可编程逻辑
页数 文件大小 规格书
37页 353K
描述
Field Programmable Gate Array, PBGA484, ROHS COMPLIANT, FBGA-484

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中文翻译

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5CEBA2F23C7N 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：BGA包装说明：BGA,
针数：484Reach Compliance Code：compliant
风险等级：5.79JESD-30 代码：S-PBGA-B484
长度：23 mm端子数量：484
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
座面最大高度：2 mm最大供电电压：1.13 V
最小供电电压：1.07 V标称供电电压：1.1 V
表面贴装：YES温度等级：OTHER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmBase Number Matches：1

5CEBA2F23C7N 数据手册

 浏览型号5CEBA2F23C7N的Datasheet PDF文件第31页浏览型号5CEBA2F23C7N的Datasheet PDF文件第32页浏览型号5CEBA2F23C7N的Datasheet PDF文件第33页浏览型号5CEBA2F23C7N的Datasheet PDF文件第34页浏览型号5CEBA2F23C7N的Datasheet PDF文件第35页浏览型号5CEBA2F23C7N的Datasheet PDF文件第37页 
Cyclone V Device Overview  
CV-51001 | 2018.05.07  
Date  
Version  
Changes  
•
•
•
Updated HPS I/O for U484 (19 mm) in Table 11 with '151' for A2, A4, A5  
and A6.  
Updated Memory (Kb) for Maximum Resource Counts for Cyclone V SE A4  
and A6, SX C4 and C6, ST D6 devices.  
Updated FPGA PLL for Maximum Resource Counts for Cyclone V SE A2, SX  
C2, devices.  
•
•
Removed '36 x 36' from the Variable-Precision DSP Block.  
Updated Variable-precision DSP Blocks and 18 x 18 Multiplier for  
Maximum Resource Counts for Cyclone V SX C4 device.  
•
•
•
•
Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.  
Updated Figure 7 which shows the I/O vertical migration table.  
Updated Table 17 for Cyclone V SX C4 device.  
Updated Embedded Memory Capacity and Distribution table for Cyclone V  
SE A4 and A6, SX C4 and C6, ST D6 devices.  
•
•
Removed 'Counter reconfiguration' from the PLL Features.  
Updated Low-Power Serial Transceivers by replacing 5 Gbps with  
6.144 Gbps.  
•
•
•
Removed 'Distributed Memory' symbol.  
Updated the Capability in Table 22 of Backplane support to '6.144 Gbps'.  
Updated Capability in Table 22 of Ring oscillator transmit PLLs with  
6.144 Gbps.  
•
•
Updated the PCS Support in Table 23 from 5 Gbps to '6 Gbps'.  
Updated the Data Rates (Gbps) in Table 23 of 3 Gbps and 6 Gbps Basic to  
'6.144 Gbps'.  
•
•
Updated the Data Rates (Gbps) in Table 23 of CPRI 4.1 to '6.144 Gbps'.  
Clarified that partial reconfiguration is an advanced feature. Contact Altera  
for support of the feature.  
December 2012  
2012.12.28  
2012.11.19  
•
•
•
Updated the pin counts for the MBGA packages.  
Updated the GPIO and transceiver counts for the MBGA packages.  
Updated the GPIO counts for the U484 package of the Cyclone V E A9, GX  
C9, and GT D9 devices.  
•
Updated the vertical migration table for vertical migration of the U484  
packages.  
•
•
Updated the MLAB supported programmable widths at 32 bits depth.  
November 2012  
Added new MBGA packages and additional U484 packages for Cyclone V E,  
GX, and GT.  
•
•
•
•
•
•
Added ordering code for five-transceiver devices for Cyclone V GT and ST.  
Updated the vertical migration table to add MBGA packages.  
Added performance information for HPS memory controller.  
Removed DDR3U support.  
Updated Cyclone V ST speed grade information.  
Added information on maximum transceiver channel usage restrictions for  
PCI Gen2 and CPRI at 4.9152 Gbps transmit jitter compliance.  
•
•
Added note on the differences between GPIO reported in Overview with  
User I/O numbers shown in the Quartus II software.  
Updated template.  
July 2012  
June 2012  
2.1  
2.0  
Added support for PCIe Gen2 x4 lane configuration (PCIe-compatible)  
•
•
Restructured the document.  
Added the “Embedded Memory Capacity” and “Embedded Memory  
Configurations” sections.  
•
•
Added Table 1, Table 3, Table 16, Table 19, and Table 20.  
Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9, Table  
10, Table 11, Table 12, Table 13, Table 14, Table 17, and Table 18.  
continued...  
Cyclone V Device Overview  
36  
1...3334353637

中文翻译

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