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5CEBA2F23C7N PDF预览

5CEBA2F23C7N

更新时间： 2024-01-21 16:02:50
品牌 Logo 应用领域
阿尔特拉 - ALTERA 栅可编程逻辑
页数 文件大小 规格书
37页 353K
描述
Field Programmable Gate Array, PBGA484, ROHS COMPLIANT, FBGA-484

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中文翻译

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5CEBA2F23C7N 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：BGA包装说明：BGA,
针数：484Reach Compliance Code：compliant
风险等级：5.79JESD-30 代码：S-PBGA-B484
长度：23 mm端子数量：484
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
座面最大高度：2 mm最大供电电压：1.13 V
最小供电电压：1.07 V标称供电电压：1.1 V
表面贴装：YES温度等级：OTHER
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：23 mmBase Number Matches：1

5CEBA2F23C7N 数据手册

 浏览型号5CEBA2F23C7N的Datasheet PDF文件第28页浏览型号5CEBA2F23C7N的Datasheet PDF文件第29页浏览型号5CEBA2F23C7N的Datasheet PDF文件第30页浏览型号5CEBA2F23C7N的Datasheet PDF文件第32页浏览型号5CEBA2F23C7N的Datasheet PDF文件第33页浏览型号5CEBA2F23C7N的Datasheet PDF文件第34页 
Cyclone V Device Overview  
CV-51001 | 2018.05.07  
Note:  
Although the FPGA fabric and HPS are on separate power domains, the HPS must  
remain powered up during operation while the FPGA fabric can be powered up or down  
as required.  
Related Information  
Cyclone V Device Family Pin Connection Guidelines  
Provides detailed information about power supply pin connection guidelines and  
power regulator sharing.  
Hardware and Software Development  
For hardware development, you can configure the HPS and connect your soft logic in  
the FPGA fabric to the HPS interfaces using the Platform Designer (Standard) system  
integration tool in the Intel Quartus Prime software.  
For software development, the Arm-based SoC devices inherit the rich software  
development ecosystem available for the Arm Cortex-A9 MPCore processor. The  
software development process for Intel SoCs follows the same steps as those for other  
SoC devices from other manufacturers. Support for Linux, VxWorks®, and other  
operating systems is available for the SoCs. For more information on the operating  
systems support availability, contact the Intel sales team.  
You can begin device-specific firmware and software development on the Intel SoC  
Virtual Target. The Virtual Target is a fast PC-based functional simulation of a target  
development system—a model of a complete development board that runs on a PC.  
The Virtual Target enables the development of device-specific production software that  
can run unmodified on actual hardware.  
Related Information  
International Altera Sales Support Offices  
Dynamic and Partial Reconfiguration  
The Cyclone V devices support dynamic reconfiguration and partial reconfiguration.  
Dynamic Reconfiguration  
The dynamic reconfiguration feature allows you to dynamically change the transceiver  
data rates, PMA settings, or protocols of a channel, without affecting data transfer on  
adjacent channels. This feature is ideal for applications that require on-the-fly  
multiprotocol or multirate support. You can reconfigure the PMA and PCS blocks with  
dynamic reconfiguration.  
Partial Reconfiguration  
Note:  
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices  
with the "SC" suffix in the part number. For device availability and ordering, contact  
your local Intel sales representatives.  
Partial reconfiguration allows you to reconfigure part of the device while other sections  
of the device remain operational. This capability is important in systems with critical  
uptime requirements because it allows you to make updates or adjust functionality  
without disrupting services.  
Cyclone V Device Overview  
31  
 
 
 
 
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