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5CEBA2F17C6 PDF预览

5CEBA2F17C6

更新时间: 2024-01-01 21:22:32
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
64页 1355K
描述
Field Programmable Gate Array, PBGA256, FBGA-256

5CEBA2F17C6 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LBGA, BGA256,16X16,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2
JESD-30 代码:S-PBGA-B256长度:17 mm
输入次数:128逻辑单元数量:25000
输出次数:128端子数量:256
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.1,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.55 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.13 V
最小供电电压:1.07 V标称供电电压:1.1 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:17 mm
Base Number Matches:1

5CEBA2F17C6 数据手册

 浏览型号5CEBA2F17C6的Datasheet PDF文件第58页浏览型号5CEBA2F17C6的Datasheet PDF文件第59页浏览型号5CEBA2F17C6的Datasheet PDF文件第60页浏览型号5CEBA2F17C6的Datasheet PDF文件第61页浏览型号5CEBA2F17C6的Datasheet PDF文件第63页浏览型号5CEBA2F17C6的Datasheet PDF文件第64页 
Page 62  
Document Revision History  
Table 64. Document Revision History (Part 2 of 3)  
Date  
Version  
Changes  
Added “HPS PLL Specifications”.  
Added Table 23, Table 35, and Table 36.  
Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25,  
Table 28, Table 34, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43,  
Table 44, Table 45, Table 46, Table 47, and Table 53.  
October 2013  
3.5  
Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.  
Removed table: GPIO Pulse Width for Cyclone V Devices.  
Updated Table 20, Table 27, and Table 34.  
Updated “UART Interface” and “CAN Interface” sections.  
Removed the following tables:  
June 2013  
May 2013  
3.4  
3.3  
Table 45. UART Baud Rate for Cyclone V Devices  
Table 47. CAN Pulse Width for Cyclone V Devices  
Added Table 33.  
Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.  
Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26,  
Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61.  
Added HPS reset information in the “HPS Specifications” section.  
Added Table 57.  
March 2013  
3.2  
3.1  
Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.  
Updated Figure 18.  
January 2013  
Updated Table 4, Table 20, and Table 56.  
Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19,  
Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59.  
Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices.  
Added HPS information:  
Added “HPS Specifications” section.  
November 2012  
3.0  
Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40,  
Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46.  
Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11,  
Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16.  
Updated Table 3.  
Updated for the Quartus II software v12.0 release:  
Restructured document.  
Removed “Power Consumption” section.  
Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30,  
Table 31, Table 34, Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and  
Table 46.  
June 2012  
2.0  
Added Table 22, Table 23, and Table 29.  
Added Figure 1 and Figure 2.  
Added “Initialization” and “Configuration Files” sections.  
Cyclone V Device Datasheet  
December 2013 Altera Corporation  

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