Datasheet > 5AGXMA1D631C4N

5AGXMA1D631C4N

更新时间： 2022-04-17 03:18:50

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
37页	793K
描述
Arria V Device Overview

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5AGXMA1D631C4N 数据手册

AV-51001

2013.05.06

Package Plan

Table 5: Package Plan for Arria V GX Devices—Preliminary

F672

F896⁴

F1152

F1517

(40 mm)

Member

Code

(27 mm)

(35 mm)

(31 mm)

GPIO

336

—

XCVR

GPIO

416

384

—

XCVR

GPIO

—

XCVR

GPIO

—

XCVR

—

544

—

704

—

Arria V GT

This section provides the available options, maximum resource counts, and package plan for the Arria V GT

devices.

Available Options

Figure 2: Sample Ordering Code and Available Options for Arria V GT Devices—Preliminary

Transceiver Count

Package Type

Embedded Hard IPs

Maximum channels

FineLine BGA (FBGA)

Operating Temperature

Industrial (T_J= -40° C to 100° C)

1 hard PCIe and 2 hard

memory controllers

Maximum 2 hard PCIe and

4 hard memory controllers

Family Signature

5A : Arria V

Optional Suffix

Indicates specific device

options or shipment method

Family Variant

Package Code

GT : 10-Gbps transceivers

27 : 672 pins

31 : 896 pins

35 : 1,152 pins

40 : 1,517 pins

Lead-free packaging

ES : Engineering sample

FPGA Fabric

Member Code

C3 : 156K logic elements

C7 : 242K logic elements

D3 : 362K logic elements

D7 : 504K logic elements

Transceiver

Speed Grade

: 10.3125 Gbps

3 (fastest)

In the F896 package, the PCIe hard IP block on the right side of the Arria V GX A5, A7, B1, and B3 devices

support x1 for Gen1 and Gen2 data rates.

Arria V Device Overview

Altera Corporation

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