生命周期: | Obsolete | 零件包装代码: | DIE |
包装说明: | DIE, | 针数: | 11 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.84 | JESD-609代码: | e0 |
逻辑集成电路类型: | NAND GATE | 功能数量: | 1 |
输入次数: | 8 | 封装主体材料: | UNSPECIFIED |
封装代码: | DIE | 封装形式: | UNCASED CHIP |
峰值回流温度(摄氏度): | NOT SPECIFIED | 传播延迟(tpd): | 16 ns |
认证状态: | Not Qualified | 表面贴装: | YES |
技术: | CMOS | 端子面层: | TIN LEAD |
端子形式: | NO LEAD | 端子位置: | UPPER |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 总剂量: | 300k Rad(Si) V |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
5962F9863101V9X | WEDC |
获取价格 |
IC 8-INPUT NAND GATE, UUC, 0.094 X 0.094 INCH, DIE-11, Gate |
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5962F9863101VCC | INTERSIL |
获取价格 |
Radiation Hardened 8-Input NAND Gate |
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5962F9863101VCX | WEDC |
获取价格 |
NAND Gate, 1-Func, 8-Input, CMOS, SIDE BRAZED, CERAMIC, DIP-14 |
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5962F9863101VXC | INTERSIL |
获取价格 |
Radiation Hardened 8-Input NAND Gate |
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5962F9863101VXX | WEDC |
获取价格 |
IC 8-INPUT NAND GATE, CDFP, CERAMIC, DFP-14, Gate |
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5962F9863201V9A | INTERSIL |
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Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
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5962F9863201V9A | RENESAS |
获取价格 |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC16, DIE-16 |
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5962F9863201VCC | INTERSIL |
获取价格 |
Radiation Hardened Dual J-K Flip-Flop with Set and Reset |
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5962F9863201VCC | RENESAS |
获取价格 |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, SIDE |
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5962F9863201VEC | ETC |
获取价格 |
J-K-Type Flip-Flop |
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