Datasheet > 5962F9583402QXC

5962F9583402QXC

更新时间： 2024-02-22 01:17:15

品牌	Logo	应用领域
艾法斯 - AEROFLEX		接收机
页数	文件大小	规格书
11页	81K
描述
Quad Receiver

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5962F9583402QXC 技术参数

生命周期：	Obsolete	包装说明：	DFP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
Is Samacsys：	N	输入特性：	DIFFERENTIAL
接口集成电路类型：	LINE RECEIVER	接口标准：	EIA-644; TIA-644; IEEE 1596.3
功能数量：	4	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	DFP	封装形式：	FLATPACK
认证状态：	Not Qualified	最大接收延迟：	8 ns
接收器位数：	4	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	2.921 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	1.27 mm	端子位置：	DUAL
总剂量：	300k Rad(Si) V	宽度：	6.731 mm
Base Number Matches：	1

5962F9583402QXC 数据手册

APPLICATIONS INFORMATION

The UT54LVDS032 receiver’s intended use is primarily in an

uncomplicated point-to-point configuration as is shown in

Figure 3. This configuration provides a clean signaling

environment for quick edge rates of the drivers. The receiver is

connected to the driver through a balanced media which may be

a standard twisted pair cable, a parallel pair cable, or simply

PCB traces. Typically, the characteristic impedance of the media

is in the range of 100W. A termination resistor of 100W should

be selected to match the media and is located as close to the

receiver input pins as possible. The termination resistor converts

the current sourced by the driver into voltages that are detected

by the receiver. Other configurations are possible such as a

multi-receiver configuration, but the effects of a mid-stream

connector(s), cable stub(s), and other impedance discontinuities,

as well as ground shifting, noise margin limits, and total

termination loading must be taken into account.

IN1-

IN1+

IN4-

OUT1

IN4+

UT54LVDS032

Receiver

OUT4

OUT2

IN2+

OUT3

IN3+

IN2-

IN3-

Figure 2. UT54LVDS032 Pinout

TRUTH TABLE

ENABLE

1/4 UT54LVDS032

DATA

Enables

Input

R_IN+- R_IN-

Output

RT 100W

INPUT

1/4 UT54LVDS031

DATA

OUTPUT

R_OUT

All other combinations

of ENABLE inputs

V_ID> 0.1V

V_ID< -0.1V

Figure 3. Point-to-Point Application

Full Fail-safe

OPEN/SHORT or

Terminated

The UT54LVDS032 differential line receiver is capable of

detecting signals as low as 100mV, over a + 1V common-mode

range centered around +1.2V. This is related to the driver offset

voltage which is typically +1.2V. The driven signal is centered

around this voltage and may shift+1V around this center point.

The +1V shifting may be the result of a ground potential

difference between the driver’s ground reference and the

receiver’s ground reference, the common-mode effects of

coupled noise or a combination of the two. Both receiver input

pins should honor their specified operating input voltage range

of 0V to +2.4V (measured from each pin to ground).

PIN DESCRIPTION

Pin No.

Name

Description

2, 6, 10, 14

R_IN+

Non-inverting receiver input pin

Inverting receiver input pin

Receiver output pin

1, 7, 9, 15

3, 5, 11, 13

R_IN-

R_OUT

Active high enable pin, OR-ed

with EN

Active low enable pin, OR-ed

with EN

V_DD

V_SS

Power supply pin, +5V + 10%

Ground pin

123 4 5 6 7...11

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5962F9583402QXXC	AEROFLEX	Quad Receiver	获取价格
5962F9583402VXA	AEROFLEX	Quad Receiver	获取价格
5962F9583402VXC	AEROFLEX	Quad Receiver	获取价格
5962F9583402VXX	AEROFLEX	Quad Receiver	获取价格

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