Datasheet > 5962F1120102VXA

5962F1120102VXA

更新时间： 2023-12-06 20:12:15

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
36页	746K
描述
Synchronous SRAM

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5962F1120102VXA 数据手册

CYRS1543AV18

CYRS1545AV18

Manufacturing Flow

Step

Screen

Method

Requirement

Wafer lot acceptance test

Internal visual

TM 5007

2010, Condition A

100%

Serialization

Temperature cycling

Constant acceleration

1010, Condition C, 50 cycles minimum

2001, YI orientation only

Condition TBD (package in design)

2020 Condition A

Particle impact noise detection (PIND)

Radiographic (X-Ray)

100%

2012, one view (Y-1 orientation) only

In accordance with applicable Cypress specification

1015, Condition D

Pre burn in electrical parameters

100%

10 Dynamic burn in

240 hours at 125 °C or 120 hours at 150 °C minimum

11 Interim (Post dynamic burn in) electricals

12 Static burn in

In accordance with applicable Cypress device specifications

100%

1015, Condition C, 72 hours at 150 °C or 144 hours at 125 °C

minimum

13 Interim (post static burn in) electricals

In accordance with applicable Cypress device specifications

5% overall, 3% functional parameters at 25 °C

100%

14 Percentage defective allowable (PDA)

calculation

All lots

15 Final electrical test

a. Static tests

In accordance with applicable Cypress device specifications

100%

(1) 25 °C

5005, Table I, Subgroup 1

5005, Table I, Subgroup 2, 3

(2) –55 °C and +125 °C

b. Functional tests

(1) 25 C

5005, Table I, Subgroup 7

5005, Table I, Subgroup 8a, 8b

5005, Table I, Subgroup 9

1014

(2) –55 °C and +125 °C

c. Switching test at 25 °C

16 Seal (fine and gross leak test)

17 External visual

18 Wafer lot specific life test (Group C)

100%

2009

Mil-PRF 38535, Appendix B, section B.4.2.c

All wafer lots

Radiation Hardened Design

Neutron Soft Error Immunity

The single event latch up (SEL) immunity is improved by a

radiation hardened design technique developed by Cypress

called RadStop. This design mitigation technique allows the SEL

performance to achieve radiation hard performance levels.

Test

Conditions

Parameter Description

Typ Max* Unit

LSBU

LMBU

SEL

Logical

single-bit

upsets

25 °C

320 368 FIT/

Logical

multi-bit

upsets

0.01 FIT/

Single event

latch up

125 °C

0.1

FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

statistical  , 95% confidence limit calculation. For more details refer to

Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of

Terrestrial Failure Rates”

Document Number: 001-60007 Rev. *N

Page 4 of 35

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