AD14060/AD14060L
off-module memory and peripherals (see Figure 5). T his port
consists of the complete external port bus of the SHARC, bused
together in common among the four SHARCs.
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the Bus-Request
(BR) line corresponding to its ID, while monitoring all others.
BR1–BR4 are used within the AD14060/AD14060L, while BR5
and BR6 can be used for expansion. All bus requests (BR1–BR6)
are included in the module I/O.
T he 4-gigaword off-module address space is included in the
ADSP-14060’s unified address space. Addressing of external
memory devices is facilitated by each SH ARC internally de-
coding the high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. T he AD14060/
AD14060L also supports programmable memory wait states and
external memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold and disable
time requirements.
T wo different priority schemes, fixed and rotating, are available
to resolve competing bus requests. The RPBA pin selects which
scheme is used: when RPBA is high, rotating priority bus arbitra-
tion is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating P riority Arbitration Exam ple
H ardware P rocessor ID s
Cycle ID 1 ID 2
ID 3
ID 4 ID 5 ID 6
Link P or t I/O
Each individual SHARC features six 4-bit link ports that facili-
tate SHARC-to-SHARC communication and external I/O inter-
facing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either 4 or 8 bits per cycle.
T he link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
1
2
3
4
5
M
4
4
5 BR
1 BR
1
2 BR
3
1
1
2
4
4
2
2
3
5
5
3
3
Initial Priority Assignments
Final Priority Assignments
5 BR M-BR
5 BR
M
M
1
3
4 BR
M
2
NOT ES
1–5 = Assigned Priority.
M = Bus Mastership (in that cycle).
BR = Requesting Bus Mastership with BRx.
T he AD14060/AD14060L optimizes the link port connections
internally, and brings a total of twelve of the link ports off-mod-
ule for user-defined system connections. Internally, each SHARC
has a connection to the other three SHARCs with a dedicated
link port interface. T hus, each SHARC can directly interface
with its nearest and next-nearest neighbor. T he remaining three
link ports from each SHARC are brought out independently
from each SH ARC. A maximum of 480 MBytes/s link port
bandwidth is then available off of the AD14060/AD14060L.
T he link port connections are detailed in Figure 4.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle only occurs when the
current bus master deasserts its BR line and one of the slave
SHARCs asserts its BR line. T he bus master can therefore re-
tain bus mastership by keeping its BR line asserted. When the
bus master deasserts its BR line, and no other BR line is as-
serted, then the master will not lose any bus cycles. When more
than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all of the BR lines, and therefore
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. An example bus
transition sequence is shown in T able I.
1
3
4
1
3
4
5
2
5
2
SHARC_A
SHARC_B
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating priority
scheme, it is also possible to limit the number of cycles the
master can control the bus. T he AD14060/AD14060L also
provides the option of using the Core Priority Access (CPA)
mode of the SHARC. Using the CPA signal allows external bus
accesses by the core processor of a slave SHARC to take priority
over ongoing DMA transfers. Also, each SHARC can broadcast
write to all other SHARCs simultaneously, allowing the imple-
mentation of reflective semaphores.
0
0
0
0
1
3
4
1
3
4
2
5
2
5
SHARC_D
SHARC_C
T he bus master can communicate with slave SHARCs by writ-
ing messages to their internal IOP registers. T he MSRG0–
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores and resource shar-
ing between the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. T his causes an immediate high priority interrupt on the
slave which, when serviced, will cause it to branch to the speci-
fied service routine.
Figure 4. Link Port Connections
Link port 4, the boot link port, is brought off independently
from each SH ARC. Individual booting is then allowed, or
chained link port booting is possible as described under “Link
Port Booting.”
Link port data is packed into 32-bit or 48-bit words, and can
be directly read by the SH ARC core processor or DMA-
transferred to on-SH ARC memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. T ransfers are programmable as either transmit or
O ff-Module Mem or y and P er ipher als Inter face
The AD14060/AD14060L’s external port provides the interface to
receive.
REV. A
–4–
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