UC1854
UC2854
UC3854
PIN DESCRIPTIONS
(Pin Numbers Refer to DIL Packages)
Gnd (Pin 1) (ground): All voltages are measured with re- VRMS (Pin 8) (RMS line voltage): The output of a boost
spect to Gnd. VCC and REF should be bypassed directly PWM is proportional to the input voltage, so when the line
voltage into a low-bandwidth boost PWM voltage regula-
tor changes, the output will change immediately and
slowly recover to the regulated level. For these devices,
the VRMS input compensates for line voltage changes if it
is connected to a voltage proportional to the RMS input
line voltage. For best control, the VRMS voltage should
stay between 1.5V and 3.5V.
to Gnd with an 0.1µF or larger ceramic capacitor. The tim-
ing capacitor discharge current also returns to this pin, so
the lead from the oscillator timing capacitor to Gnd should
also be as short and as direct as possible.
PKLMT (Pin 2) (peak limit): The threshold for PKLMT is
0.0V. Connect this input to the negative voltage on the
current sense resistor as shown in Figure 1. Use a resis-
tor to REF to offset the negative current sense signal up
to Gnd.
REF (Pin 9) (voltage reference output): REF is the output
of an accurate 7.5V voltage reference. This output is ca-
pable of delivering 10mA to peripheral circuitry and is in-
ternally short circuit current limited. REF is disabled and
will remain at 0V when VCC is low or when ENA is low.
CA Out (Pin 3) (current amplifier output): This is the out-
put of a wide-bandwidth op amp that senses line current
and commands the pulse width modulator (PWM) to force
the correct current. This output can swing close to Gnd,
allowing the PWM to force zero duty cycle when neces-
Bypass REF to Gnd with an 0.1µF or larger ceramic ca-
pacitor for best stability.
sary. The current amplifier will remain active even if the IC ENA (Pin 10) (enable): ENA is a logic input that will en-
is disabled. The current amplifier output stage is an NPN able the PWM output, voltage reference, and oscillator.
emitter follower pull-up and an 8k resistor to ground.
ENA also will release the soft start clamp, allowing SS to
rise. When unused, connect ENA to a +5V supply or pull
ENA high with a 22k resistor. The ENA pin is not intended
to be used as a high speed shutdown to the PWM output.
ISENSE (Pin 4) (current sense minus): This is the inverting
input to the current amplifier. This input and the non-in-
verting input Mult Out remain functional down to and be-
low Gnd. Care should be taken to avoid taking these
V
SENSE
(Pin 11) (voltage amplifier inverting input): This is
inputs below –0.5V, because they are protected with di- normally connected to a feedback network and to the
odes to Gnd. boost converter output through a divider network.
Mult Out (Pin 5) (multiplier output and current sense RSET (Pin 12) (oscillator charging current and multiplier
plus): The output of the analog multiplier and the non-in- limit set): A resistor from RSET to ground will program os-
verting input of the current amplifier are connected to- cillator charging current and maximum multiplier output.
gether at Mult Out. The cautions about taking ISENSE Multiplier output current will not exceed 3.75V divided by
below –0.5V also apply to Mult Out. As the multiplier out- the resistor from RSET to ground.
put is a current, this is a high impedance input similar to
SS (Pin 13) (soft start): SS will remain at Gnd as long as
ISENSE, so the current amplifier can be configured as a
the IC is disabled or VCC is too low. SS will pull up to over
differential amplifier to reject Gnd noise. Figure 1 shows
8V by an internal 14µA current source when both VCC be-
an example of using the current amplifier differentially.
comes valid and the IC is enabled. SS will act as the ref-
IAC (Pin 6) (input AC current): This input to the analog
multiplier is a current. The multiplier is tailored for very
low distortion from this current input (IAC) to Mult Out, so
this is the only multiplier input that should be used for
sensing instantaneous line voltage. The nominal voltage
on IAC is 6V, so in addition to a resistor from IAC to recti-
fied 60Hz, connect a resistor from IAC to REF. If the resis-
tor to REF is one fourth of the value of the resistor to the
rectifier, then the 6V offset will be cancelled, and the line
current will have minimal cross-over distortion.
erence input to the voltage amplifier if SS is below REF.
With a large capacitor from SS to Gnd, the reference to
the voltage regulating amplifier will rise slowly, and in-
crease the PWM duty cycle slowly. In the event of a dis-
able command or a supply dropout, SS will quickly
discharge to ground and disable the PWM.
CT (Pin 14) (oscillator timing capacitor): A capacitor from
CT to Gnd will set the PWM oscillator frequency accord-
ing to this relationship:
1.25
F =
VA Out (Pin 7) (voltage amplifier output): This is the out-
put of the op amp that regulates output voltage. Like the
current amplifier, the voltage amplifier will stay active
even if the IC is disabled with either ENA or VCC. This
means that large feedback capacitors across the amplifier
will stay charged through momentary disable cycles. Volt-
age amplifier output levels below 1V will inhibit multiplier
output. The voltage amplifier output is internally limited to
approximately 5.8V to prevent overshoot. The voltage
amplifier output stage is an NPN emitter follower pull-up
and an 8k resistor to ground.
RSET × CT
VCC (Pin 15) (positive supply voltage): Connect VCC to a
stable source of at least 20mA above 17V for normal op-
eration. Also bypass VCC directly to Gnd to absorb supply
current spikes required to charge external MOSFET gate
capacitances. To prevent inadequate GT Drv signals,
these devices will be inhibited unless VCC exceeds the
upper under-voltage lockout threshold and remains
above the lower threshold.
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